jannik/c3lingo-interpreter-unit
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c3lingo-interpreter-unit/schematics/c3lingo_unit-assembly/c3lingo_unit-channel/c3lingo_unit-channel.kicad_pcb

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PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(kicad_pcb (version 20171130) (host pcbnew "(5.1.10-1-10_14)")
Schematic: Bugfixes, VU meter draft, first development PCB draft
2020-11-02 00:00:47 +00:00
(general
(thickness 1.6)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(drawings 58)
(tracks 569)
Schematic: Bugfixes, VU meter draft, first development PCB draft
2020-11-02 00:00:47 +00:00
(zones 0)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(modules 126)
(nets 80)
Schematic: Bugfixes, VU meter draft, first development PCB draft
2020-11-02 00:00:47 +00:00
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(page A4 portrait)
final fixes for first prototype PCB order
2020-11-12 23:40:18 +00:00
(title_block
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(title "c3lingo interpeter unit -- channel strip")
(date 2021-05-30)
Main: Summing design flaw fixed; better headphone vol. range - Multiple R and C value adaptions - Line Input: No relevant difference between INA134 and own circuit -> LM833 chosen - Signal busses/ summing module inputs fixed - TODO: On-Air Button - TODO: Update PCB layout
2020-12-13 21:02:02 +00:00
(rev v0.2)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(company "Jannik Beyerstedt (jtbx)")
(comment 1 "Prototype 1")
final fixes for first prototype PCB order
2020-11-12 23:40:18 +00:00
)
Schematic: Bugfixes, VU meter draft, first development PCB draft
2020-11-02 00:00:47 +00:00
(layers
(0 F.Cu signal)
(31 B.Cu signal)
(32 B.Adhes user)
(33 F.Adhes user)
(34 B.Paste user)
(35 F.Paste user)
(36 B.SilkS user)
(37 F.SilkS user)
(38 B.Mask user)
(39 F.Mask user)
(40 Dwgs.User user)
(41 Cmts.User user)
(42 Eco1.User user)
(43 Eco2.User user)
(44 Edge.Cuts user)
(45 Margin user)
(46 B.CrtYd user)
(47 F.CrtYd user)
(48 B.Fab user)
(49 F.Fab user)
)
(setup
(last_trace_width 0.25)
(user_trace_width 0.25)
(user_trace_width 1)
final fixes for first prototype PCB order
2020-11-12 23:40:18 +00:00
(trace_clearance 0.25)
Schematic: Bugfixes, VU meter draft, first development PCB draft
2020-11-02 00:00:47 +00:00
(zone_clearance 0.508)
(zone_45_only no)
(trace_min 0.2)
(via_size 0.6)
(via_drill 0.3)
(via_min_size 0.4)
(via_min_drill 0.3)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(user_via 0.6 0.3)
(user_via 0.8 0.6)
Schematic: Bugfixes, VU meter draft, first development PCB draft
2020-11-02 00:00:47 +00:00
(uvia_size 0.3)
(uvia_drill 0.1)
(uvias_allowed no)
(uvia_min_size 0.2)
(uvia_min_drill 0.1)
(edge_width 0.05)
(segment_width 0.2)
(pcb_text_width 0.3)
(pcb_text_size 1.5 1.5)
(mod_edge_width 0.12)
(mod_text_size 1 1)
(mod_text_width 0.15)
Main: Summing design flaw fixed; better headphone vol. range - Multiple R and C value adaptions - Line Input: No relevant difference between INA134 and own circuit -> LM833 chosen - Signal busses/ summing module inputs fixed - TODO: On-Air Button - TODO: Update PCB layout
2020-12-13 21:02:02 +00:00
(pad_size 1.7 1.7)
(pad_drill 1)
Schematic: Bugfixes, VU meter draft, first development PCB draft
2020-11-02 00:00:47 +00:00
(pad_to_mask_clearance 0)
(aux_axis_origin 0 0)
(visible_elements FFFFFF7F)
(pcbplotparams
final fixes for first prototype PCB order
2020-11-12 23:40:18 +00:00
(layerselection 0x010f0_ffffffff)
(usegerberextensions true)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(usegerberattributes false)
Schematic: Bugfixes, VU meter draft, first development PCB draft
2020-11-02 00:00:47 +00:00
(usegerberadvancedattributes true)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(creategerberjobfile false)
Schematic: Bugfixes, VU meter draft, first development PCB draft
2020-11-02 00:00:47 +00:00
(excludeedgelayer true)
(linewidth 0.100000)
(plotframeref false)
(viasonmask false)
(mode 1)
(useauxorigin false)
(hpglpennumber 1)
(hpglpenspeed 20)
(hpglpendiameter 15.000000)
(psnegative false)
(psa4output false)
(plotreference true)
(plotvalue true)
(plotinvisibletext false)
(padsonsilk false)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(subtractmaskfromsilk true)
Schematic: Bugfixes, VU meter draft, first development PCB draft
2020-11-02 00:00:47 +00:00
(outputformat 1)
(mirror false)
(drillshape 0)
(scaleselection 1)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(outputdirectory "c3lingo_unit-channel-gerber"))
Schematic: Bugfixes, VU meter draft, first development PCB draft
2020-11-02 00:00:47 +00:00
)
(net 0 "")
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
(net 1 -15V)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(net 2 +15V)
(net 3 GND)
(net 4 "Net-(C103-Pad2)")
(net 5 "Net-(C106-Pad2)")
(net 6 "Net-(C107-Pad2)")
(net 7 "Net-(C107-Pad1)")
(net 8 "Net-(C108-Pad1)")
(net 9 "Net-(C109-Pad1)")
(net 10 "Net-(C110-Pad2)")
(net 11 "Net-(C110-Pad1)")
(net 12 V_Phant)
(net 13 "Net-(C112-Pad2)")
(net 14 "Net-(C113-Pad2)")
(net 15 "Net-(C113-Pad1)")
(net 16 "Net-(C114-Pad2)")
(net 17 "Net-(C114-Pad1)")
(net 18 "Net-(C119-Pad2)")
(net 19 "Net-(C119-Pad1)")
(net 20 "Net-(C120-Pad1)")
(net 21 "Net-(D101-Pad2)")
(net 22 "Net-(D101-Pad1)")
(net 23 V_LED)
(net 24 "Net-(D106-Pad1)")
(net 25 "Net-(D107-Pad1)")
(net 26 "Net-(D108-Pad1)")
(net 27 "Net-(D109-Pad1)")
(net 28 "Net-(D110-Pad1)")
(net 29 "Net-(D111-Pad1)")
(net 30 "Net-(D112-Pad1)")
(net 31 "Net-(D113-Pad1)")
(net 32 "Net-(D114-Pad1)")
(net 33 "Net-(D115-Pad1)")
(net 34 "Net-(D116-Pad1)")
(net 35 "Net-(D117-Pad1)")
(net 36 "Net-(D118-Pad2)")
(net 37 "Net-(D118-Pad1)")
(net 38 GNDREF)
(net 39 /Monitor_OthersB)
(net 40 /Monitor_OthersA)
(net 41 /Monitor_Stage)
(net 42 "Net-(R101-Pad2)")
(net 43 "Net-(R103-Pad1)")
(net 44 "Net-(R105-Pad1)")
(net 45 "Net-(R108-Pad2)")
(net 46 "Net-(R109-Pad2)")
(net 47 "Net-(R113-Pad2)")
(net 48 "Net-(R117-Pad2)")
(net 49 "Net-(R118-Pad1)")
(net 50 "Net-(R119-Pad2)")
(net 51 "Net-(R121-Pad2)")
(net 52 "Net-(R122-Pad2)")
(net 53 "Net-(R123-Pad2)")
(net 54 "Net-(R124-Pad2)")
(net 55 "Net-(R125-Pad2)")
(net 56 "Net-(R126-Pad2)")
(net 57 "Net-(R127-Pad2)")
(net 58 "Net-(R128-Pad2)")
(net 59 "Net-(R129-Pad2)")
(net 60 "Net-(R130-Pad2)")
(net 61 "Net-(R131-Pad2)")
(net 62 "Net-(R132-Pad2)")
(net 63 "Net-(R134-Pad2)")
(net 64 "Net-(R135-Pad2)")
(net 65 "Net-(R136-Pad2)")
(net 66 "Net-(R137-Pad2)")
(net 67 "Net-(R138-Pad2)")
(net 68 "Net-(R139-Pad2)")
(net 69 "Net-(R140-Pad2)")
(net 70 "Net-(R141-Pad2)")
(net 71 "Net-(R142-Pad2)")
(net 72 "Net-(R143-Pad2)")
(net 73 "Net-(R144-Pad2)")
(net 74 "Net-(R145-Pad2)")
(net 75 /PreampOut)
(net 76 SumOut)
(net 77 MicPreOut)
(net 78 AmpIn)
(net 79 MicGainIn)
Schematic: Bugfixes, VU meter draft, first development PCB draft
2020-11-02 00:00:47 +00:00
(net_class Default "This is the default net class."
final fixes for first prototype PCB order
2020-11-12 23:40:18 +00:00
(clearance 0.25)
Schematic: Bugfixes, VU meter draft, first development PCB draft
2020-11-02 00:00:47 +00:00
(trace_width 0.25)
(via_dia 0.6)
(via_drill 0.3)
(uvia_dia 0.3)
(uvia_drill 0.1)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(add_net /Monitor_OthersA)
(add_net /Monitor_OthersB)
(add_net /Monitor_Stage)
(add_net /PreampOut)
(add_net AmpIn)
(add_net MicGainIn)
(add_net MicPreOut)
(add_net "Net-(C103-Pad2)")
(add_net "Net-(C106-Pad2)")
(add_net "Net-(C107-Pad1)")
(add_net "Net-(C107-Pad2)")
(add_net "Net-(C108-Pad1)")
(add_net "Net-(C109-Pad1)")
(add_net "Net-(C110-Pad1)")
(add_net "Net-(C110-Pad2)")
(add_net "Net-(C112-Pad2)")
(add_net "Net-(C113-Pad1)")
(add_net "Net-(C113-Pad2)")
(add_net "Net-(C114-Pad1)")
(add_net "Net-(C114-Pad2)")
(add_net "Net-(C119-Pad1)")
(add_net "Net-(C119-Pad2)")
(add_net "Net-(C120-Pad1)")
(add_net "Net-(D101-Pad1)")
(add_net "Net-(D101-Pad2)")
(add_net "Net-(D106-Pad1)")
(add_net "Net-(D107-Pad1)")
(add_net "Net-(D108-Pad1)")
(add_net "Net-(D109-Pad1)")
(add_net "Net-(D110-Pad1)")
(add_net "Net-(D111-Pad1)")
(add_net "Net-(D112-Pad1)")
(add_net "Net-(D113-Pad1)")
(add_net "Net-(D114-Pad1)")
(add_net "Net-(D115-Pad1)")
(add_net "Net-(D116-Pad1)")
(add_net "Net-(D117-Pad1)")
(add_net "Net-(D118-Pad1)")
(add_net "Net-(D118-Pad2)")
(add_net "Net-(R101-Pad2)")
(add_net "Net-(R103-Pad1)")
(add_net "Net-(R105-Pad1)")
(add_net "Net-(R108-Pad2)")
(add_net "Net-(R109-Pad2)")
(add_net "Net-(R113-Pad2)")
(add_net "Net-(R117-Pad2)")
(add_net "Net-(R118-Pad1)")
(add_net "Net-(R119-Pad2)")
(add_net "Net-(R121-Pad2)")
(add_net "Net-(R122-Pad2)")
(add_net "Net-(R123-Pad2)")
(add_net "Net-(R124-Pad2)")
(add_net "Net-(R125-Pad2)")
(add_net "Net-(R126-Pad2)")
(add_net "Net-(R127-Pad2)")
(add_net "Net-(R128-Pad2)")
(add_net "Net-(R129-Pad2)")
(add_net "Net-(R130-Pad2)")
(add_net "Net-(R131-Pad2)")
(add_net "Net-(R132-Pad2)")
(add_net "Net-(R134-Pad2)")
(add_net "Net-(R135-Pad2)")
(add_net "Net-(R136-Pad2)")
(add_net "Net-(R137-Pad2)")
(add_net "Net-(R138-Pad2)")
(add_net "Net-(R139-Pad2)")
(add_net "Net-(R140-Pad2)")
(add_net "Net-(R141-Pad2)")
(add_net "Net-(R142-Pad2)")
(add_net "Net-(R143-Pad2)")
(add_net "Net-(R144-Pad2)")
(add_net "Net-(R145-Pad2)")
(add_net SumOut)
Schematic: Bugfixes, VU meter draft, first development PCB draft
2020-11-02 00:00:47 +00:00
)
(net_class Power ""
final fixes for first prototype PCB order
2020-11-12 23:40:18 +00:00
(clearance 0.3)
Schematic: Bugfixes, VU meter draft, first development PCB draft
2020-11-02 00:00:47 +00:00
(trace_width 1)
(via_dia 0.8)
(via_drill 0.6)
(uvia_dia 0.3)
(uvia_drill 0.1)
(add_net +15V)
(add_net -15V)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(add_net GND)
(add_net GNDREF)
(add_net V_LED)
(add_net V_Phant)
Schematic: Bugfixes, VU meter draft, first development PCB draft
2020-11-02 00:00:47 +00:00
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(module c3lingo_unit-footprints:mouse-bite-3mm-6mm (layer F.Cu) (tedit 60B4033A) (tstamp 60B9ABB2)
(at 113 171.5)
(fp_text reference REF** (at 2 2) (layer F.SilkS)
Main: Summing design flaw fixed; better headphone vol. range - Multiple R and C value adaptions - Line Input: No relevant difference between INA134 and own circuit -> LM833 chosen - Signal busses/ summing module inputs fixed - TODO: On-Air Button - TODO: Update PCB layout
2020-12-13 21:02:02 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(fp_text value mouse-bite-3mm-6mm (at 1.5 -2) (layer F.Fab)
Main: Summing design flaw fixed; better headphone vol. range - Multiple R and C value adaptions - Line Input: No relevant difference between INA134 and own circuit -> LM833 chosen - Signal busses/ summing module inputs fixed - TODO: On-Air Button - TODO: Update PCB layout
2020-12-13 21:02:02 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(pad "" np_thru_hole circle (at 4.5 1.25) (size 0.5 0.5) (drill 0.5) (layers *.Cu *.Mask))
(pad "" np_thru_hole circle (at 3.5 1.25) (size 0.5 0.5) (drill 0.5) (layers *.Cu *.Mask))
(pad "" np_thru_hole circle (at 3.5 -1.25) (size 0.5 0.5) (drill 0.5) (layers *.Cu *.Mask))
(pad "" np_thru_hole circle (at 4.5 -1.25) (size 0.5 0.5) (drill 0.5) (layers *.Cu *.Mask))
(pad "" np_thru_hole circle (at 1.5 -1.25) (size 0.5 0.5) (drill 0.5) (layers *.Cu *.Mask))
(pad "" np_thru_hole circle (at 1.5 1.25) (size 0.5 0.5) (drill 0.5) (layers *.Cu *.Mask))
(pad "" np_thru_hole circle (at 2.5 1.25) (size 0.5 0.5) (drill 0.5) (layers *.Cu *.Mask))
(pad "" np_thru_hole circle (at 2.5 -1.25) (size 0.5 0.5) (drill 0.5) (layers *.Cu *.Mask))
(pad "" np_thru_hole circle (at -0.5 1.25) (size 0.5 0.5) (drill 0.5) (layers *.Cu *.Mask))
(pad "" np_thru_hole circle (at 0.5 1.25) (size 0.5 0.5) (drill 0.5) (layers *.Cu *.Mask))
(pad "" np_thru_hole circle (at 0.5 -1.25) (size 0.5 0.5) (drill 0.5) (layers *.Cu *.Mask))
(pad "" np_thru_hole circle (at -0.5 -1.25) (size 0.5 0.5) (drill 0.5) (layers *.Cu *.Mask))
)
(module c3lingo_unit-footprints:mouse-bite-3mm-6mm (layer F.Cu) (tedit 60B4033A) (tstamp 60B9A9D0)
(at 58 171.5)
(fp_text reference REF** (at 2 2) (layer F.SilkS)
Main: Summing design flaw fixed; better headphone vol. range - Multiple R and C value adaptions - Line Input: No relevant difference between INA134 and own circuit -> LM833 chosen - Signal busses/ summing module inputs fixed - TODO: On-Air Button - TODO: Update PCB layout
2020-12-13 21:02:02 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(fp_text value mouse-bite-3mm-6mm (at 1.5 -2) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
Main: Summing design flaw fixed; better headphone vol. range - Multiple R and C value adaptions - Line Input: No relevant difference between INA134 and own circuit -> LM833 chosen - Signal busses/ summing module inputs fixed - TODO: On-Air Button - TODO: Update PCB layout
2020-12-13 21:02:02 +00:00
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(pad "" np_thru_hole circle (at 4.5 1.25) (size 0.5 0.5) (drill 0.5) (layers *.Cu *.Mask))
(pad "" np_thru_hole circle (at 3.5 1.25) (size 0.5 0.5) (drill 0.5) (layers *.Cu *.Mask))
(pad "" np_thru_hole circle (at 3.5 -1.25) (size 0.5 0.5) (drill 0.5) (layers *.Cu *.Mask))
(pad "" np_thru_hole circle (at 4.5 -1.25) (size 0.5 0.5) (drill 0.5) (layers *.Cu *.Mask))
(pad "" np_thru_hole circle (at 1.5 -1.25) (size 0.5 0.5) (drill 0.5) (layers *.Cu *.Mask))
(pad "" np_thru_hole circle (at 1.5 1.25) (size 0.5 0.5) (drill 0.5) (layers *.Cu *.Mask))
(pad "" np_thru_hole circle (at 2.5 1.25) (size 0.5 0.5) (drill 0.5) (layers *.Cu *.Mask))
(pad "" np_thru_hole circle (at 2.5 -1.25) (size 0.5 0.5) (drill 0.5) (layers *.Cu *.Mask))
(pad "" np_thru_hole circle (at -0.5 1.25) (size 0.5 0.5) (drill 0.5) (layers *.Cu *.Mask))
(pad "" np_thru_hole circle (at 0.5 1.25) (size 0.5 0.5) (drill 0.5) (layers *.Cu *.Mask))
(pad "" np_thru_hole circle (at 0.5 -1.25) (size 0.5 0.5) (drill 0.5) (layers *.Cu *.Mask))
(pad "" np_thru_hole circle (at -0.5 -1.25) (size 0.5 0.5) (drill 0.5) (layers *.Cu *.Mask))
Main: Summing design flaw fixed; better headphone vol. range - Multiple R and C value adaptions - Line Input: No relevant difference between INA134 and own circuit -> LM833 chosen - Signal busses/ summing module inputs fixed - TODO: On-Air Button - TODO: Update PCB layout
2020-12-13 21:02:02 +00:00
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(module Capacitor_THT:CP_Radial_D6.3mm_P2.50mm (layer F.Cu) (tedit 5AE50EF0) (tstamp 5FA9DB7B)
(at 107.95 205.09 270)
(descr "CP, Radial series, Radial, pin pitch=2.50mm, , diameter=6.3mm, Electrolytic Capacitor")
(tags "CP Radial series Radial pin pitch 2.50mm diameter 6.3mm Electrolytic Capacitor")
(path /5FB6C2ED)
(fp_text reference C110 (at 1.25 3.81 90) (layer F.SilkS)
Main: Summing design flaw fixed; better headphone vol. range - Multiple R and C value adaptions - Line Input: No relevant difference between INA134 and own circuit -> LM833 chosen - Signal busses/ summing module inputs fixed - TODO: On-Air Button - TODO: Update PCB layout
2020-12-13 21:02:02 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(fp_text value "220uF lowESR" (at 1.25 4.4 90) (layer F.Fab)
Main: Summing design flaw fixed; better headphone vol. range - Multiple R and C value adaptions - Line Input: No relevant difference between INA134 and own circuit -> LM833 chosen - Signal busses/ summing module inputs fixed - TODO: On-Air Button - TODO: Update PCB layout
2020-12-13 21:02:02 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(fp_circle (center 1.25 0) (end 4.4 0) (layer F.Fab) (width 0.1))
(fp_circle (center 1.25 0) (end 4.52 0) (layer F.SilkS) (width 0.12))
(fp_circle (center 1.25 0) (end 4.65 0) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.443972 -1.3735) (end -0.813972 -1.3735) (layer F.Fab) (width 0.1))
(fp_line (start -1.128972 -1.6885) (end -1.128972 -1.0585) (layer F.Fab) (width 0.1))
(fp_line (start 1.25 -3.23) (end 1.25 3.23) (layer F.SilkS) (width 0.12))
(fp_line (start 1.29 -3.23) (end 1.29 3.23) (layer F.SilkS) (width 0.12))
(fp_line (start 1.33 -3.23) (end 1.33 3.23) (layer F.SilkS) (width 0.12))
(fp_line (start 1.37 -3.228) (end 1.37 3.228) (layer F.SilkS) (width 0.12))
(fp_line (start 1.41 -3.227) (end 1.41 3.227) (layer F.SilkS) (width 0.12))
(fp_line (start 1.45 -3.224) (end 1.45 3.224) (layer F.SilkS) (width 0.12))
(fp_line (start 1.49 -3.222) (end 1.49 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 1.49 1.04) (end 1.49 3.222) (layer F.SilkS) (width 0.12))
(fp_line (start 1.53 -3.218) (end 1.53 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 1.53 1.04) (end 1.53 3.218) (layer F.SilkS) (width 0.12))
(fp_line (start 1.57 -3.215) (end 1.57 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 1.57 1.04) (end 1.57 3.215) (layer F.SilkS) (width 0.12))
(fp_line (start 1.61 -3.211) (end 1.61 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 1.61 1.04) (end 1.61 3.211) (layer F.SilkS) (width 0.12))
(fp_line (start 1.65 -3.206) (end 1.65 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 1.65 1.04) (end 1.65 3.206) (layer F.SilkS) (width 0.12))
(fp_line (start 1.69 -3.201) (end 1.69 -1.04) (layer F.SilkS) (width 0.12))
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(fp_text user %R (at 1.25 0 90) (layer F.Fab)
Main: Summing design flaw fixed; better headphone vol. range - Multiple R and C value adaptions - Line Input: No relevant difference between INA134 and own circuit -> LM833 chosen - Signal busses/ summing module inputs fixed - TODO: On-Air Button - TODO: Update PCB layout
2020-12-13 21:02:02 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(pad 2 thru_hole circle (at 2.5 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 10 "Net-(C110-Pad2)"))
(pad 1 thru_hole rect (at 0 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 11 "Net-(C110-Pad1)"))
(model ${KISYS3DMOD}/Capacitor_THT.3dshapes/CP_Radial_D6.3mm_P2.50mm.wrl
Main: Summing design flaw fixed; better headphone vol. range - Multiple R and C value adaptions - Line Input: No relevant difference between INA134 and own circuit -> LM833 chosen - Signal busses/ summing module inputs fixed - TODO: On-Air Button - TODO: Update PCB layout
2020-12-13 21:02:02 +00:00
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(module Capacitor_THT:CP_Radial_D6.3mm_P2.50mm (layer B.Cu) (tedit 5AE50EF0) (tstamp 60B1C2AB)
(at 116.84 123.19)
(descr "CP, Radial series, Radial, pin pitch=2.50mm, , diameter=6.3mm, Electrolytic Capacitor")
(tags "CP Radial series Radial pin pitch 2.50mm diameter 6.3mm Electrolytic Capacitor")
(path /60B42924)
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(fp_circle (center 1.25 0) (end 4.52 0) (layer B.SilkS) (width 0.12))
(fp_circle (center 1.25 0) (end 4.4 0) (layer B.Fab) (width 0.1))
(fp_text user %R (at 1.25 0 180) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(pad 2 thru_hole circle (at 2.5 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 3 GND))
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
(pad 1 thru_hole rect (at 0 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(net 20 "Net-(C120-Pad1)"))
(model ${KISYS3DMOD}/Capacitor_THT.3dshapes/CP_Radial_D6.3mm_P2.50mm.wrl
Main: Summing design flaw fixed; better headphone vol. range - Multiple R and C value adaptions - Line Input: No relevant difference between INA134 and own circuit -> LM833 chosen - Signal busses/ summing module inputs fixed - TODO: On-Air Button - TODO: Update PCB layout
2020-12-13 21:02:02 +00:00
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(module Capacitor_THT:CP_Radial_D5.0mm_P2.00mm (layer B.Cu) (tedit 5AE50EF0) (tstamp 60B1C1D6)
(at 99.79 151.13 180)
(descr "CP, Radial series, Radial, pin pitch=2.00mm, , diameter=5mm, Electrolytic Capacitor")
(tags "CP Radial series Radial pin pitch 2.00mm diameter 5mm Electrolytic Capacitor")
(path /60B42977)
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(fp_line (start 1 2.58) (end 1 1.04) (layer B.SilkS) (width 0.12))
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(fp_line (start -0.883605 1.3375) (end -0.883605 0.8375) (layer B.Fab) (width 0.1))
(fp_line (start -1.133605 1.0875) (end -0.633605 1.0875) (layer B.Fab) (width 0.1))
(fp_circle (center 1 0) (end 3.75 0) (layer B.CrtYd) (width 0.05))
(fp_circle (center 1 0) (end 3.62 0) (layer B.SilkS) (width 0.12))
(fp_circle (center 1 0) (end 3.5 0) (layer B.Fab) (width 0.1))
(fp_text user %R (at 1 0) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(pad 2 thru_hole circle (at 2 0 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 18 "Net-(C119-Pad2)"))
(pad 1 thru_hole rect (at 0 0 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 19 "Net-(C119-Pad1)"))
(model ${KISYS3DMOD}/Capacitor_THT.3dshapes/CP_Radial_D5.0mm_P2.00mm.wrl
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
Main: Summing design flaw fixed; better headphone vol. range - Multiple R and C value adaptions - Line Input: No relevant difference between INA134 and own circuit -> LM833 chosen - Signal busses/ summing module inputs fixed - TODO: On-Air Button - TODO: Update PCB layout
2020-12-13 21:02:02 +00:00
)
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(module Capacitor_THT:CP_Radial_D6.3mm_P2.50mm (layer F.Cu) (tedit 5AE50EF0) (tstamp 5F9FD759)
(at 88.9 177.15 180)
(descr "CP, Radial series, Radial, pin pitch=2.50mm, , diameter=6.3mm, Electrolytic Capacitor")
(tags "CP Radial series Radial pin pitch 2.50mm diameter 6.3mm Electrolytic Capacitor")
(path /5F8514CB)
(fp_text reference C118 (at 5.08 0 90) (layer F.SilkS)
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(fp_text value 100uF (at 1.25 4.4) (layer F.Fab)
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(fp_line (start -1.935241 -2.154) (end -1.935241 -1.524) (layer F.SilkS) (width 0.12))
(fp_line (start -2.250241 -1.839) (end -1.620241 -1.839) (layer F.SilkS) (width 0.12))
(fp_line (start 4.491 -0.402) (end 4.491 0.402) (layer F.SilkS) (width 0.12))
(fp_line (start 4.451 -0.633) (end 4.451 0.633) (layer F.SilkS) (width 0.12))
(fp_line (start 4.411 -0.802) (end 4.411 0.802) (layer F.SilkS) (width 0.12))
(fp_line (start 4.371 -0.94) (end 4.371 0.94) (layer F.SilkS) (width 0.12))
(fp_line (start 4.331 -1.059) (end 4.331 1.059) (layer F.SilkS) (width 0.12))
(fp_line (start 4.291 -1.165) (end 4.291 1.165) (layer F.SilkS) (width 0.12))
(fp_line (start 4.251 -1.262) (end 4.251 1.262) (layer F.SilkS) (width 0.12))
(fp_line (start 4.211 -1.35) (end 4.211 1.35) (layer F.SilkS) (width 0.12))
(fp_line (start 4.171 -1.432) (end 4.171 1.432) (layer F.SilkS) (width 0.12))
(fp_line (start 4.131 -1.509) (end 4.131 1.509) (layer F.SilkS) (width 0.12))
(fp_line (start 4.091 -1.581) (end 4.091 1.581) (layer F.SilkS) (width 0.12))
(fp_line (start 4.051 -1.65) (end 4.051 1.65) (layer F.SilkS) (width 0.12))
(fp_line (start 4.011 -1.714) (end 4.011 1.714) (layer F.SilkS) (width 0.12))
(fp_line (start 3.971 -1.776) (end 3.971 1.776) (layer F.SilkS) (width 0.12))
(fp_line (start 3.931 -1.834) (end 3.931 1.834) (layer F.SilkS) (width 0.12))
(fp_line (start 3.891 -1.89) (end 3.891 1.89) (layer F.SilkS) (width 0.12))
(fp_line (start 3.851 -1.944) (end 3.851 1.944) (layer F.SilkS) (width 0.12))
(fp_line (start 3.811 -1.995) (end 3.811 1.995) (layer F.SilkS) (width 0.12))
(fp_line (start 3.771 -2.044) (end 3.771 2.044) (layer F.SilkS) (width 0.12))
(fp_line (start 3.731 -2.092) (end 3.731 2.092) (layer F.SilkS) (width 0.12))
(fp_line (start 3.691 -2.137) (end 3.691 2.137) (layer F.SilkS) (width 0.12))
(fp_line (start 3.651 -2.182) (end 3.651 2.182) (layer F.SilkS) (width 0.12))
(fp_line (start 3.611 -2.224) (end 3.611 2.224) (layer F.SilkS) (width 0.12))
(fp_line (start 3.571 -2.265) (end 3.571 2.265) (layer F.SilkS) (width 0.12))
(fp_line (start 3.531 1.04) (end 3.531 2.305) (layer F.SilkS) (width 0.12))
(fp_line (start 3.531 -2.305) (end 3.531 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 3.491 1.04) (end 3.491 2.343) (layer F.SilkS) (width 0.12))
(fp_line (start 3.491 -2.343) (end 3.491 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 3.451 1.04) (end 3.451 2.38) (layer F.SilkS) (width 0.12))
(fp_line (start 3.451 -2.38) (end 3.451 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 3.411 1.04) (end 3.411 2.416) (layer F.SilkS) (width 0.12))
(fp_line (start 3.411 -2.416) (end 3.411 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 3.371 1.04) (end 3.371 2.45) (layer F.SilkS) (width 0.12))
(fp_line (start 3.371 -2.45) (end 3.371 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 3.331 1.04) (end 3.331 2.484) (layer F.SilkS) (width 0.12))
(fp_line (start 3.331 -2.484) (end 3.331 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 3.291 1.04) (end 3.291 2.516) (layer F.SilkS) (width 0.12))
(fp_line (start 3.291 -2.516) (end 3.291 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 3.251 1.04) (end 3.251 2.548) (layer F.SilkS) (width 0.12))
(fp_line (start 3.251 -2.548) (end 3.251 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 3.211 1.04) (end 3.211 2.578) (layer F.SilkS) (width 0.12))
(fp_line (start 3.211 -2.578) (end 3.211 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 3.171 1.04) (end 3.171 2.607) (layer F.SilkS) (width 0.12))
(fp_line (start 3.171 -2.607) (end 3.171 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 3.131 1.04) (end 3.131 2.636) (layer F.SilkS) (width 0.12))
(fp_line (start 3.131 -2.636) (end 3.131 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 3.091 1.04) (end 3.091 2.664) (layer F.SilkS) (width 0.12))
(fp_line (start 3.091 -2.664) (end 3.091 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 3.051 1.04) (end 3.051 2.69) (layer F.SilkS) (width 0.12))
(fp_line (start 3.051 -2.69) (end 3.051 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 3.011 1.04) (end 3.011 2.716) (layer F.SilkS) (width 0.12))
(fp_line (start 3.011 -2.716) (end 3.011 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 2.971 1.04) (end 2.971 2.742) (layer F.SilkS) (width 0.12))
(fp_line (start 2.971 -2.742) (end 2.971 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 2.931 1.04) (end 2.931 2.766) (layer F.SilkS) (width 0.12))
(fp_line (start 2.931 -2.766) (end 2.931 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 2.891 1.04) (end 2.891 2.79) (layer F.SilkS) (width 0.12))
(fp_line (start 2.891 -2.79) (end 2.891 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 2.851 1.04) (end 2.851 2.812) (layer F.SilkS) (width 0.12))
(fp_line (start 2.851 -2.812) (end 2.851 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 2.811 1.04) (end 2.811 2.834) (layer F.SilkS) (width 0.12))
(fp_line (start 2.811 -2.834) (end 2.811 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 2.771 1.04) (end 2.771 2.856) (layer F.SilkS) (width 0.12))
(fp_line (start 2.771 -2.856) (end 2.771 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 2.731 1.04) (end 2.731 2.876) (layer F.SilkS) (width 0.12))
(fp_line (start 2.731 -2.876) (end 2.731 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 2.691 1.04) (end 2.691 2.896) (layer F.SilkS) (width 0.12))
(fp_line (start 2.691 -2.896) (end 2.691 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 2.651 1.04) (end 2.651 2.916) (layer F.SilkS) (width 0.12))
(fp_line (start 2.651 -2.916) (end 2.651 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 2.611 1.04) (end 2.611 2.934) (layer F.SilkS) (width 0.12))
(fp_line (start 2.611 -2.934) (end 2.611 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 2.571 1.04) (end 2.571 2.952) (layer F.SilkS) (width 0.12))
(fp_line (start 2.571 -2.952) (end 2.571 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 2.531 1.04) (end 2.531 2.97) (layer F.SilkS) (width 0.12))
(fp_line (start 2.531 -2.97) (end 2.531 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 2.491 1.04) (end 2.491 2.986) (layer F.SilkS) (width 0.12))
(fp_line (start 2.491 -2.986) (end 2.491 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 2.451 1.04) (end 2.451 3.002) (layer F.SilkS) (width 0.12))
(fp_line (start 2.451 -3.002) (end 2.451 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 2.411 1.04) (end 2.411 3.018) (layer F.SilkS) (width 0.12))
(fp_line (start 2.411 -3.018) (end 2.411 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 2.371 1.04) (end 2.371 3.033) (layer F.SilkS) (width 0.12))
(fp_line (start 2.371 -3.033) (end 2.371 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 2.331 1.04) (end 2.331 3.047) (layer F.SilkS) (width 0.12))
(fp_line (start 2.331 -3.047) (end 2.331 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 2.291 1.04) (end 2.291 3.061) (layer F.SilkS) (width 0.12))
(fp_line (start 2.291 -3.061) (end 2.291 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 2.251 1.04) (end 2.251 3.074) (layer F.SilkS) (width 0.12))
(fp_line (start 2.251 -3.074) (end 2.251 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 2.211 1.04) (end 2.211 3.086) (layer F.SilkS) (width 0.12))
(fp_line (start 2.211 -3.086) (end 2.211 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 2.171 1.04) (end 2.171 3.098) (layer F.SilkS) (width 0.12))
(fp_line (start 2.171 -3.098) (end 2.171 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 2.131 1.04) (end 2.131 3.11) (layer F.SilkS) (width 0.12))
(fp_line (start 2.131 -3.11) (end 2.131 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 2.091 1.04) (end 2.091 3.121) (layer F.SilkS) (width 0.12))
(fp_line (start 2.091 -3.121) (end 2.091 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 2.051 1.04) (end 2.051 3.131) (layer F.SilkS) (width 0.12))
(fp_line (start 2.051 -3.131) (end 2.051 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 2.011 1.04) (end 2.011 3.141) (layer F.SilkS) (width 0.12))
(fp_line (start 2.011 -3.141) (end 2.011 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 1.971 1.04) (end 1.971 3.15) (layer F.SilkS) (width 0.12))
(fp_line (start 1.971 -3.15) (end 1.971 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 1.93 1.04) (end 1.93 3.159) (layer F.SilkS) (width 0.12))
(fp_line (start 1.93 -3.159) (end 1.93 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 1.89 1.04) (end 1.89 3.167) (layer F.SilkS) (width 0.12))
(fp_line (start 1.89 -3.167) (end 1.89 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 1.85 1.04) (end 1.85 3.175) (layer F.SilkS) (width 0.12))
(fp_line (start 1.85 -3.175) (end 1.85 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 1.81 1.04) (end 1.81 3.182) (layer F.SilkS) (width 0.12))
(fp_line (start 1.81 -3.182) (end 1.81 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 1.77 1.04) (end 1.77 3.189) (layer F.SilkS) (width 0.12))
(fp_line (start 1.77 -3.189) (end 1.77 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 1.73 1.04) (end 1.73 3.195) (layer F.SilkS) (width 0.12))
(fp_line (start 1.73 -3.195) (end 1.73 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 1.69 1.04) (end 1.69 3.201) (layer F.SilkS) (width 0.12))
(fp_line (start 1.69 -3.201) (end 1.69 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 1.65 1.04) (end 1.65 3.206) (layer F.SilkS) (width 0.12))
(fp_line (start 1.65 -3.206) (end 1.65 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 1.61 1.04) (end 1.61 3.211) (layer F.SilkS) (width 0.12))
(fp_line (start 1.61 -3.211) (end 1.61 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 1.57 1.04) (end 1.57 3.215) (layer F.SilkS) (width 0.12))
(fp_line (start 1.57 -3.215) (end 1.57 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 1.53 1.04) (end 1.53 3.218) (layer F.SilkS) (width 0.12))
(fp_line (start 1.53 -3.218) (end 1.53 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 1.49 1.04) (end 1.49 3.222) (layer F.SilkS) (width 0.12))
(fp_line (start 1.49 -3.222) (end 1.49 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 1.45 -3.224) (end 1.45 3.224) (layer F.SilkS) (width 0.12))
(fp_line (start 1.41 -3.227) (end 1.41 3.227) (layer F.SilkS) (width 0.12))
(fp_line (start 1.37 -3.228) (end 1.37 3.228) (layer F.SilkS) (width 0.12))
(fp_line (start 1.33 -3.23) (end 1.33 3.23) (layer F.SilkS) (width 0.12))
(fp_line (start 1.29 -3.23) (end 1.29 3.23) (layer F.SilkS) (width 0.12))
(fp_line (start 1.25 -3.23) (end 1.25 3.23) (layer F.SilkS) (width 0.12))
(fp_line (start -1.128972 -1.6885) (end -1.128972 -1.0585) (layer F.Fab) (width 0.1))
(fp_line (start -1.443972 -1.3735) (end -0.813972 -1.3735) (layer F.Fab) (width 0.1))
(fp_circle (center 1.25 0) (end 4.65 0) (layer F.CrtYd) (width 0.05))
(fp_circle (center 1.25 0) (end 4.52 0) (layer F.SilkS) (width 0.12))
(fp_circle (center 1.25 0) (end 4.4 0) (layer F.Fab) (width 0.1))
(fp_text user %R (at 1.25 0) (layer F.Fab)
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(pad 2 thru_hole circle (at 2.5 0 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 3 GND))
(pad 1 thru_hole rect (at 0 0 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 2 +15V))
(model ${KISYS3DMOD}/Capacitor_THT.3dshapes/CP_Radial_D6.3mm_P2.50mm.wrl
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
Main: Summing design flaw fixed; better headphone vol. range - Multiple R and C value adaptions - Line Input: No relevant difference between INA134 and own circuit -> LM833 chosen - Signal busses/ summing module inputs fixed - TODO: On-Air Button - TODO: Update PCB layout
2020-12-13 21:02:02 +00:00
)
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(module Capacitor_THT:CP_Radial_D6.3mm_P2.50mm (layer F.Cu) (tedit 5AE50EF0) (tstamp 5FA9DAAF)
(at 114.3 212.71 270)
(descr "CP, Radial series, Radial, pin pitch=2.50mm, , diameter=6.3mm, Electrolytic Capacitor")
(tags "CP Radial series Radial pin pitch 2.50mm diameter 6.3mm Electrolytic Capacitor")
(path /5FD130B1)
(fp_text reference C108 (at 1.25 -4.4 90) (layer F.SilkS)
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(fp_text value 100uF (at 1.25 4.4 90) (layer F.Fab)
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(fp_line (start -1.935241 -2.154) (end -1.935241 -1.524) (layer F.SilkS) (width 0.12))
(fp_line (start -2.250241 -1.839) (end -1.620241 -1.839) (layer F.SilkS) (width 0.12))
(fp_line (start 4.491 -0.402) (end 4.491 0.402) (layer F.SilkS) (width 0.12))
(fp_line (start 4.451 -0.633) (end 4.451 0.633) (layer F.SilkS) (width 0.12))
(fp_line (start 4.411 -0.802) (end 4.411 0.802) (layer F.SilkS) (width 0.12))
(fp_line (start 4.371 -0.94) (end 4.371 0.94) (layer F.SilkS) (width 0.12))
(fp_line (start 4.331 -1.059) (end 4.331 1.059) (layer F.SilkS) (width 0.12))
(fp_line (start 4.291 -1.165) (end 4.291 1.165) (layer F.SilkS) (width 0.12))
(fp_line (start 4.251 -1.262) (end 4.251 1.262) (layer F.SilkS) (width 0.12))
(fp_line (start 4.211 -1.35) (end 4.211 1.35) (layer F.SilkS) (width 0.12))
(fp_line (start 4.171 -1.432) (end 4.171 1.432) (layer F.SilkS) (width 0.12))
(fp_line (start 4.131 -1.509) (end 4.131 1.509) (layer F.SilkS) (width 0.12))
(fp_line (start 4.091 -1.581) (end 4.091 1.581) (layer F.SilkS) (width 0.12))
(fp_line (start 4.051 -1.65) (end 4.051 1.65) (layer F.SilkS) (width 0.12))
(fp_line (start 4.011 -1.714) (end 4.011 1.714) (layer F.SilkS) (width 0.12))
(fp_line (start 3.971 -1.776) (end 3.971 1.776) (layer F.SilkS) (width 0.12))
(fp_line (start 3.931 -1.834) (end 3.931 1.834) (layer F.SilkS) (width 0.12))
(fp_line (start 3.891 -1.89) (end 3.891 1.89) (layer F.SilkS) (width 0.12))
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(model ${KISYS3DMOD}/Capacitor_THT.3dshapes/CP_Radial_D6.3mm_P2.50mm.wrl
Main: Summing design flaw fixed; better headphone vol. range - Multiple R and C value adaptions - Line Input: No relevant difference between INA134 and own circuit -> LM833 chosen - Signal busses/ summing module inputs fixed - TODO: On-Air Button - TODO: Update PCB layout
2020-12-13 21:02:02 +00:00
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(module Capacitor_THT:CP_Radial_D6.3mm_P2.50mm (layer F.Cu) (tedit 5AE50EF0) (tstamp 5FA9D9CE)
(at 119.38 186.04)
(descr "CP, Radial series, Radial, pin pitch=2.50mm, , diameter=6.3mm, Electrolytic Capacitor")
(tags "CP Radial series Radial pin pitch 2.50mm diameter 6.3mm Electrolytic Capacitor")
(path /60184128)
(fp_text reference C102 (at 1.25 -4.4) (layer F.SilkS)
Main: Summing design flaw fixed; better headphone vol. range - Multiple R and C value adaptions - Line Input: No relevant difference between INA134 and own circuit -> LM833 chosen - Signal busses/ summing module inputs fixed - TODO: On-Air Button - TODO: Update PCB layout
2020-12-13 21:02:02 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(fp_text value 100uF (at 1.25 4.4) (layer F.Fab)
Main: Summing design flaw fixed; better headphone vol. range - Multiple R and C value adaptions - Line Input: No relevant difference between INA134 and own circuit -> LM833 chosen - Signal busses/ summing module inputs fixed - TODO: On-Air Button - TODO: Update PCB layout
2020-12-13 21:02:02 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
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(fp_line (start -1.443972 -1.3735) (end -0.813972 -1.3735) (layer F.Fab) (width 0.1))
(fp_circle (center 1.25 0) (end 4.65 0) (layer F.CrtYd) (width 0.05))
(fp_circle (center 1.25 0) (end 4.52 0) (layer F.SilkS) (width 0.12))
(fp_circle (center 1.25 0) (end 4.4 0) (layer F.Fab) (width 0.1))
(fp_text user %R (at 1.25 0) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 2 thru_hole circle (at 2.5 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 3 GND))
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
(pad 1 thru_hole rect (at 0 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(net 2 +15V))
(model ${KISYS3DMOD}/Capacitor_THT.3dshapes/CP_Radial_D6.3mm_P2.50mm.wrl
Main: Summing design flaw fixed; better headphone vol. range - Multiple R and C value adaptions - Line Input: No relevant difference between INA134 and own circuit -> LM833 chosen - Signal busses/ summing module inputs fixed - TODO: On-Air Button - TODO: Update PCB layout
2020-12-13 21:02:02 +00:00
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(module Capacitor_THT:CP_Radial_D6.3mm_P2.50mm (layer F.Cu) (tedit 5AE50EF0) (tstamp 5F9FD543)
(at 86.4 205.09)
(descr "CP, Radial series, Radial, pin pitch=2.50mm, , diameter=6.3mm, Electrolytic Capacitor")
(tags "CP Radial series Radial pin pitch 2.50mm diameter 6.3mm Electrolytic Capacitor")
(path /5F863B13)
(fp_text reference C101 (at -2.58 0 90) (layer F.SilkS)
Main: Summing design flaw fixed; better headphone vol. range - Multiple R and C value adaptions - Line Input: No relevant difference between INA134 and own circuit -> LM833 chosen - Signal busses/ summing module inputs fixed - TODO: On-Air Button - TODO: Update PCB layout
2020-12-13 21:02:02 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(fp_text value 100uF (at 1.25 4.4) (layer F.Fab)
Main: Summing design flaw fixed; better headphone vol. range - Multiple R and C value adaptions - Line Input: No relevant difference between INA134 and own circuit -> LM833 chosen - Signal busses/ summing module inputs fixed - TODO: On-Air Button - TODO: Update PCB layout
2020-12-13 21:02:02 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
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(fp_line (start 1.971 -3.15) (end 1.971 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 1.93 1.04) (end 1.93 3.159) (layer F.SilkS) (width 0.12))
(fp_line (start 1.93 -3.159) (end 1.93 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 1.89 1.04) (end 1.89 3.167) (layer F.SilkS) (width 0.12))
(fp_line (start 1.89 -3.167) (end 1.89 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 1.85 1.04) (end 1.85 3.175) (layer F.SilkS) (width 0.12))
(fp_line (start 1.85 -3.175) (end 1.85 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 1.81 1.04) (end 1.81 3.182) (layer F.SilkS) (width 0.12))
(fp_line (start 1.81 -3.182) (end 1.81 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 1.77 1.04) (end 1.77 3.189) (layer F.SilkS) (width 0.12))
(fp_line (start 1.77 -3.189) (end 1.77 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 1.73 1.04) (end 1.73 3.195) (layer F.SilkS) (width 0.12))
(fp_line (start 1.73 -3.195) (end 1.73 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 1.69 1.04) (end 1.69 3.201) (layer F.SilkS) (width 0.12))
(fp_line (start 1.69 -3.201) (end 1.69 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 1.65 1.04) (end 1.65 3.206) (layer F.SilkS) (width 0.12))
(fp_line (start 1.65 -3.206) (end 1.65 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 1.61 1.04) (end 1.61 3.211) (layer F.SilkS) (width 0.12))
(fp_line (start 1.61 -3.211) (end 1.61 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 1.57 1.04) (end 1.57 3.215) (layer F.SilkS) (width 0.12))
(fp_line (start 1.57 -3.215) (end 1.57 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 1.53 1.04) (end 1.53 3.218) (layer F.SilkS) (width 0.12))
(fp_line (start 1.53 -3.218) (end 1.53 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 1.49 1.04) (end 1.49 3.222) (layer F.SilkS) (width 0.12))
(fp_line (start 1.49 -3.222) (end 1.49 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 1.45 -3.224) (end 1.45 3.224) (layer F.SilkS) (width 0.12))
(fp_line (start 1.41 -3.227) (end 1.41 3.227) (layer F.SilkS) (width 0.12))
(fp_line (start 1.37 -3.228) (end 1.37 3.228) (layer F.SilkS) (width 0.12))
(fp_line (start 1.33 -3.23) (end 1.33 3.23) (layer F.SilkS) (width 0.12))
(fp_line (start 1.29 -3.23) (end 1.29 3.23) (layer F.SilkS) (width 0.12))
(fp_line (start 1.25 -3.23) (end 1.25 3.23) (layer F.SilkS) (width 0.12))
(fp_line (start -1.128972 -1.6885) (end -1.128972 -1.0585) (layer F.Fab) (width 0.1))
(fp_line (start -1.443972 -1.3735) (end -0.813972 -1.3735) (layer F.Fab) (width 0.1))
(fp_circle (center 1.25 0) (end 4.65 0) (layer F.CrtYd) (width 0.05))
(fp_circle (center 1.25 0) (end 4.52 0) (layer F.SilkS) (width 0.12))
(fp_circle (center 1.25 0) (end 4.4 0) (layer F.Fab) (width 0.1))
(fp_text user %R (at 1.25 0) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 2 thru_hole circle (at 2.5 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 1 -15V))
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
(pad 1 thru_hole rect (at 0 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(net 3 GND))
(model ${KISYS3DMOD}/Capacitor_THT.3dshapes/CP_Radial_D6.3mm_P2.50mm.wrl
final fixes for first prototype PCB order
2020-11-12 23:40:18 +00:00
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(module MountingHole:MountingHole_3.2mm_M3 (layer F.Cu) (tedit 56D1B4CB) (tstamp 60B3EDE6)
(at 122 176)
(descr "Mounting Hole 3.2mm, no annular, M3")
(tags "mounting hole 3.2mm no annular m3")
(path /60C57E93)
(attr virtual)
(fp_text reference H306 (at 0 -4.2) (layer F.SilkS) hide
final fixes for first prototype PCB order
2020-11-12 23:40:18 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(fp_text value MountingHole (at 0 4.2) (layer F.Fab)
Main: Summing design flaw fixed; better headphone vol. range - Multiple R and C value adaptions - Line Input: No relevant difference between INA134 and own circuit -> LM833 chosen - Signal busses/ summing module inputs fixed - TODO: On-Air Button - TODO: Update PCB layout
2020-12-13 21:02:02 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(fp_circle (center 0 0) (end 3.2 0) (layer Cmts.User) (width 0.15))
(fp_circle (center 0 0) (end 3.45 0) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 0.3 0) (layer F.Fab)
final fixes for first prototype PCB order
2020-11-12 23:40:18 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(pad 1 np_thru_hole circle (at 0 0) (size 3.2 3.2) (drill 3.2) (layers *.Cu *.Mask))
)
(module MountingHole:MountingHole_3.2mm_M3 (layer F.Cu) (tedit 56D1B4CB) (tstamp 60B3EDDE)
(at 53 176)
(descr "Mounting Hole 3.2mm, no annular, M3")
(tags "mounting hole 3.2mm no annular m3")
(path /60C57BF3)
(attr virtual)
(fp_text reference H305 (at 0 -4.2) (layer F.SilkS) hide
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value MountingHole (at 0 4.2) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_circle (center 0 0) (end 3.2 0) (layer Cmts.User) (width 0.15))
(fp_circle (center 0 0) (end 3.45 0) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 0.3 0) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 1 np_thru_hole circle (at 0 0) (size 3.2 3.2) (drill 3.2) (layers *.Cu *.Mask))
)
(module TerminalBlock_Phoenix:TerminalBlock_Phoenix_PTSM-0,5-3-2.5-H-THR_1x03_P2.50mm_Horizontal (layer F.Cu) (tedit 5B294EBC) (tstamp 60B396DB)
(at 107.95 177.15 180)
(descr "Terminal Block Phoenix PTSM-0,5-3-2.5-H-THR, 3 pins, pitch 2.5mm, size 9.7x10mm^2, drill diamater 1.2mm, pad diameter 3mm, see http://www.produktinfo.conrad.com/datenblaetter/550000-574999/556441-da-01-de-LEITERPLATTENKL__PTSM_0_5__8_2_5_H_THR.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix")
(tags "THT Terminal Block Phoenix PTSM-0,5-3-2.5-H-THR pitch 2.5mm size 9.7x10mm^2 drill 1.2mm pad 3mm")
(path /60E33C38)
(fp_text reference J107 (at 2.5 -8.26) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value Interconnect (at 2.5 3.86) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 7.85 -7.7) (end -2.85 -7.7) (layer F.CrtYd) (width 0.05))
(fp_line (start 7.85 3.3) (end 7.85 -7.7) (layer F.CrtYd) (width 0.05))
(fp_line (start -2.85 3.3) (end 7.85 3.3) (layer F.CrtYd) (width 0.05))
(fp_line (start -2.85 -7.7) (end -2.85 3.3) (layer F.CrtYd) (width 0.05))
(fp_line (start -2.65 3.1) (end -0.65 3.1) (layer F.SilkS) (width 0.12))
(fp_line (start -2.65 0.86) (end -2.65 3.1) (layer F.SilkS) (width 0.12))
(fp_line (start 7.41 -7.26) (end 7.41 2.86) (layer F.SilkS) (width 0.12))
(fp_line (start -2.41 -7.26) (end -2.41 2.86) (layer F.SilkS) (width 0.12))
(fp_line (start -2.41 2.86) (end 7.41 2.86) (layer F.SilkS) (width 0.12))
(fp_line (start -2.41 -7.26) (end 7.41 -7.26) (layer F.SilkS) (width 0.12))
(fp_line (start -2.35 0.8) (end -2.35 -7.2) (layer F.Fab) (width 0.1))
(fp_line (start -0.35 2.8) (end -2.35 0.8) (layer F.Fab) (width 0.1))
(fp_line (start 7.35 2.8) (end -0.35 2.8) (layer F.Fab) (width 0.1))
(fp_line (start 7.35 -7.2) (end 7.35 2.8) (layer F.Fab) (width 0.1))
(fp_line (start -2.35 -7.2) (end 7.35 -7.2) (layer F.Fab) (width 0.1))
(fp_text user %R (at 2.5 -2.2) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 3 thru_hole oval (at 5 -5 180) (size 1.8 3) (drill 1.2) (layers *.Cu *.Mask)
(net 77 MicPreOut))
(pad 3 thru_hole oval (at 5 0 180) (size 1.8 3) (drill 1.2) (layers *.Cu *.Mask)
(net 77 MicPreOut))
(pad 2 thru_hole oval (at 2.5 -5 180) (size 1.8 3) (drill 1.2) (layers *.Cu *.Mask)
(net 78 AmpIn))
(pad 2 thru_hole oval (at 2.5 0 180) (size 1.8 3) (drill 1.2) (layers *.Cu *.Mask)
(net 78 AmpIn))
(pad 1 thru_hole rect (at 0 -5 180) (size 1.8 3) (drill 1.2) (layers *.Cu *.Mask)
(net 3 GND))
(pad 1 thru_hole rect (at 0 0 180) (size 1.8 3) (drill 1.2) (layers *.Cu *.Mask)
(net 3 GND))
(model ${KISYS3DMOD}/TerminalBlock_Phoenix.3dshapes/TerminalBlock_Phoenix_PTSM-0,5-3-2.5-H-THR_1x03_P2.50mm_Horizontal.wrl
final fixes for first prototype PCB order
2020-11-12 23:40:18 +00:00
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(module TerminalBlock_Phoenix:TerminalBlock_Phoenix_PTSM-0,5-3-2.5-H-THR_1x03_P2.50mm_Horizontal (layer B.Cu) (tedit 5B294EBC) (tstamp 60B39759)
(at 53.34 137.16 90)
(descr "Terminal Block Phoenix PTSM-0,5-3-2.5-H-THR, 3 pins, pitch 2.5mm, size 9.7x10mm^2, drill diamater 1.2mm, pad diameter 3mm, see http://www.produktinfo.conrad.com/datenblaetter/550000-574999/556441-da-01-de-LEITERPLATTENKL__PTSM_0_5__8_2_5_H_THR.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix")
(tags "THT Terminal Block Phoenix PTSM-0,5-3-2.5-H-THR pitch 2.5mm size 9.7x10mm^2 drill 1.2mm pad 3mm")
(path /60E30DA1)
(fp_text reference J108 (at 2.5 8.26 90) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value Interconnect (at 2.5 -3.86 90) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_line (start 7.85 7.7) (end -2.85 7.7) (layer B.CrtYd) (width 0.05))
(fp_line (start 7.85 -3.3) (end 7.85 7.7) (layer B.CrtYd) (width 0.05))
(fp_line (start -2.85 -3.3) (end 7.85 -3.3) (layer B.CrtYd) (width 0.05))
(fp_line (start -2.85 7.7) (end -2.85 -3.3) (layer B.CrtYd) (width 0.05))
(fp_line (start -2.65 -3.1) (end -0.65 -3.1) (layer B.SilkS) (width 0.12))
(fp_line (start -2.65 -0.86) (end -2.65 -3.1) (layer B.SilkS) (width 0.12))
(fp_line (start 7.41 7.26) (end 7.41 -2.86) (layer B.SilkS) (width 0.12))
(fp_line (start -2.41 7.26) (end -2.41 -2.86) (layer B.SilkS) (width 0.12))
(fp_line (start -2.41 -2.86) (end 7.41 -2.86) (layer B.SilkS) (width 0.12))
(fp_line (start -2.41 7.26) (end 7.41 7.26) (layer B.SilkS) (width 0.12))
(fp_line (start -2.35 -0.8) (end -2.35 7.2) (layer B.Fab) (width 0.1))
(fp_line (start -0.35 -2.8) (end -2.35 -0.8) (layer B.Fab) (width 0.1))
(fp_line (start 7.35 -2.8) (end -0.35 -2.8) (layer B.Fab) (width 0.1))
(fp_line (start 7.35 7.2) (end 7.35 -2.8) (layer B.Fab) (width 0.1))
(fp_line (start -2.35 7.2) (end 7.35 7.2) (layer B.Fab) (width 0.1))
(fp_text user %R (at 2.5 2.2 90) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(pad 3 thru_hole oval (at 5 5 90) (size 1.8 3) (drill 1.2) (layers *.Cu *.Mask)
(net 79 MicGainIn))
(pad 3 thru_hole oval (at 5 0 90) (size 1.8 3) (drill 1.2) (layers *.Cu *.Mask)
(net 79 MicGainIn))
(pad 2 thru_hole oval (at 2.5 5 90) (size 1.8 3) (drill 1.2) (layers *.Cu *.Mask)
(net 76 SumOut))
(pad 2 thru_hole oval (at 2.5 0 90) (size 1.8 3) (drill 1.2) (layers *.Cu *.Mask)
(net 76 SumOut))
(pad 1 thru_hole rect (at 0 5 90) (size 1.8 3) (drill 1.2) (layers *.Cu *.Mask)
(net 3 GND))
(pad 1 thru_hole rect (at 0 0 90) (size 1.8 3) (drill 1.2) (layers *.Cu *.Mask)
(net 3 GND))
(model ${KISYS3DMOD}/TerminalBlock_Phoenix.3dshapes/TerminalBlock_Phoenix_PTSM-0,5-3-2.5-H-THR_1x03_P2.50mm_Horizontal.wrl
final fixes for first prototype PCB order
2020-11-12 23:40:18 +00:00
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(module Connector_PinHeader_2.54mm:PinHeader_1x02_P2.54mm_Vertical (layer B.Cu) (tedit 59FED5CC) (tstamp 5F9FE1EA)
(at 54.61 80.01 270)
(descr "Through hole straight pin header, 1x02, 2.54mm pitch, single row")
(tags "Through hole pin header THT 1x02 2.54mm single row")
(path /60D151FD)
(fp_text reference SW302 (at 0 2.33 90) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value Mute_X (at 0 -4.87 90) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_line (start -0.635 1.27) (end 1.27 1.27) (layer B.Fab) (width 0.1))
(fp_line (start 1.27 1.27) (end 1.27 -3.81) (layer B.Fab) (width 0.1))
(fp_line (start 1.27 -3.81) (end -1.27 -3.81) (layer B.Fab) (width 0.1))
(fp_line (start -1.27 -3.81) (end -1.27 0.635) (layer B.Fab) (width 0.1))
(fp_line (start -1.27 0.635) (end -0.635 1.27) (layer B.Fab) (width 0.1))
(fp_line (start -1.33 -3.87) (end 1.33 -3.87) (layer B.SilkS) (width 0.12))
(fp_line (start -1.33 -1.27) (end -1.33 -3.87) (layer B.SilkS) (width 0.12))
(fp_line (start 1.33 -1.27) (end 1.33 -3.87) (layer B.SilkS) (width 0.12))
(fp_line (start -1.33 -1.27) (end 1.33 -1.27) (layer B.SilkS) (width 0.12))
(fp_line (start -1.33 0) (end -1.33 1.33) (layer B.SilkS) (width 0.12))
(fp_line (start -1.33 1.33) (end 0 1.33) (layer B.SilkS) (width 0.12))
(fp_line (start -1.8 1.8) (end -1.8 -4.35) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.8 -4.35) (end 1.8 -4.35) (layer B.CrtYd) (width 0.05))
(fp_line (start 1.8 -4.35) (end 1.8 1.8) (layer B.CrtYd) (width 0.05))
(fp_line (start 1.8 1.8) (end -1.8 1.8) (layer B.CrtYd) (width 0.05))
(fp_text user %R (at 0 -1.27 180) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(pad 2 thru_hole oval (at 0 -2.54 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 75 /PreampOut))
(pad 1 thru_hole rect (at 0 0 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 5 "Net-(C106-Pad2)"))
(model ${KISYS3DMOD}/Connector_PinHeader_2.54mm.3dshapes/PinHeader_1x02_P2.54mm_Vertical.wrl
Schematic Main: Add corrected headphone amp
2020-11-09 22:22:35 +00:00
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(module TerminalBlock_Phoenix:TerminalBlock_Phoenix_PTSM-0,5-4-2.5-H-THR_1x04_P2.50mm_Horizontal (layer F.Cu) (tedit 5B294EBC) (tstamp 60B4EB41)
(at 80.01 177.15 180)
(descr "Terminal Block Phoenix PTSM-0,5-4-2.5-H-THR, 4 pins, pitch 2.5mm, size 12.2x10mm^2, drill diamater 1.2mm, pad diameter 3mm, see http://www.produktinfo.conrad.com/datenblaetter/550000-574999/556441-da-01-de-LEITERPLATTENKL__PTSM_0_5__8_2_5_H_THR.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix")
(tags "THT Terminal Block Phoenix PTSM-0,5-4-2.5-H-THR pitch 2.5mm size 12.2x10mm^2 drill 1.2mm pad 3mm")
(path /60EDD4C9)
(fp_text reference J106 (at 3.75 -8.26) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value PowerSupply (at 3.75 3.86) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 10.35 -7.7) (end -2.85 -7.7) (layer F.CrtYd) (width 0.05))
(fp_line (start 10.35 3.3) (end 10.35 -7.7) (layer F.CrtYd) (width 0.05))
(fp_line (start -2.85 3.3) (end 10.35 3.3) (layer F.CrtYd) (width 0.05))
(fp_line (start -2.85 -7.7) (end -2.85 3.3) (layer F.CrtYd) (width 0.05))
(fp_line (start -2.65 3.1) (end -0.65 3.1) (layer F.SilkS) (width 0.12))
(fp_line (start -2.65 0.86) (end -2.65 3.1) (layer F.SilkS) (width 0.12))
(fp_line (start 9.91 -7.26) (end 9.91 2.86) (layer F.SilkS) (width 0.12))
(fp_line (start -2.41 -7.26) (end -2.41 2.86) (layer F.SilkS) (width 0.12))
(fp_line (start -2.41 2.86) (end 9.91 2.86) (layer F.SilkS) (width 0.12))
(fp_line (start -2.41 -7.26) (end 9.91 -7.26) (layer F.SilkS) (width 0.12))
(fp_line (start -2.35 0.8) (end -2.35 -7.2) (layer F.Fab) (width 0.1))
(fp_line (start -0.35 2.8) (end -2.35 0.8) (layer F.Fab) (width 0.1))
(fp_line (start 9.85 2.8) (end -0.35 2.8) (layer F.Fab) (width 0.1))
(fp_line (start 9.85 -7.2) (end 9.85 2.8) (layer F.Fab) (width 0.1))
(fp_line (start -2.35 -7.2) (end 9.85 -7.2) (layer F.Fab) (width 0.1))
(fp_text user %R (at 3.75 -2.2) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 4 thru_hole oval (at 7.5 -5 180) (size 1.8 3) (drill 1.2) (layers *.Cu *.Mask)
(net 12 V_Phant))
(pad 4 thru_hole oval (at 7.5 0 180) (size 1.8 3) (drill 1.2) (layers *.Cu *.Mask)
(net 12 V_Phant))
(pad 3 thru_hole oval (at 5 -5 180) (size 1.8 3) (drill 1.2) (layers *.Cu *.Mask)
(net 1 -15V))
(pad 3 thru_hole oval (at 5 0 180) (size 1.8 3) (drill 1.2) (layers *.Cu *.Mask)
(net 1 -15V))
(pad 2 thru_hole oval (at 2.5 -5 180) (size 1.8 3) (drill 1.2) (layers *.Cu *.Mask)
(net 2 +15V))
(pad 2 thru_hole oval (at 2.5 0 180) (size 1.8 3) (drill 1.2) (layers *.Cu *.Mask)
(net 2 +15V))
(pad 1 thru_hole rect (at 0 -5 180) (size 1.8 3) (drill 1.2) (layers *.Cu *.Mask)
(net 3 GND))
(pad 1 thru_hole rect (at 0 0 180) (size 1.8 3) (drill 1.2) (layers *.Cu *.Mask)
(net 3 GND))
(model ${KISYS3DMOD}/TerminalBlock_Phoenix.3dshapes/TerminalBlock_Phoenix_PTSM-0,5-4-2.5-H-THR_1x04_P2.50mm_Horizontal.wrl
Main: Summing design flaw fixed; better headphone vol. range - Multiple R and C value adaptions - Line Input: No relevant difference between INA134 and own circuit -> LM833 chosen - Signal busses/ summing module inputs fixed - TODO: On-Air Button - TODO: Update PCB layout
2020-12-13 21:02:02 +00:00
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(module TerminalBlock_Phoenix:TerminalBlock_Phoenix_PTSM-0,5-4-2.5-H-THR_1x04_P2.50mm_Horizontal (layer B.Cu) (tedit 5B294EBC) (tstamp 60B1C54F)
(at 69.85 53.34)
(descr "Terminal Block Phoenix PTSM-0,5-4-2.5-H-THR, 4 pins, pitch 2.5mm, size 12.2x10mm^2, drill diamater 1.2mm, pad diameter 3mm, see http://www.produktinfo.conrad.com/datenblaetter/550000-574999/556441-da-01-de-LEITERPLATTENKL__PTSM_0_5__8_2_5_H_THR.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix")
(tags "THT Terminal Block Phoenix PTSM-0,5-4-2.5-H-THR pitch 2.5mm size 12.2x10mm^2 drill 1.2mm pad 3mm")
(path /60F119DD)
(fp_text reference J103 (at 3.75 8.26) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value PowerSupply (at 3.75 -3.86) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_line (start 10.35 7.7) (end -2.85 7.7) (layer B.CrtYd) (width 0.05))
(fp_line (start 10.35 -3.3) (end 10.35 7.7) (layer B.CrtYd) (width 0.05))
(fp_line (start -2.85 -3.3) (end 10.35 -3.3) (layer B.CrtYd) (width 0.05))
(fp_line (start -2.85 7.7) (end -2.85 -3.3) (layer B.CrtYd) (width 0.05))
(fp_line (start -2.65 -3.1) (end -0.65 -3.1) (layer B.SilkS) (width 0.12))
(fp_line (start -2.65 -0.86) (end -2.65 -3.1) (layer B.SilkS) (width 0.12))
(fp_line (start 9.91 7.26) (end 9.91 -2.86) (layer B.SilkS) (width 0.12))
(fp_line (start -2.41 7.26) (end -2.41 -2.86) (layer B.SilkS) (width 0.12))
(fp_line (start -2.41 -2.86) (end 9.91 -2.86) (layer B.SilkS) (width 0.12))
(fp_line (start -2.41 7.26) (end 9.91 7.26) (layer B.SilkS) (width 0.12))
(fp_line (start -2.35 -0.8) (end -2.35 7.2) (layer B.Fab) (width 0.1))
(fp_line (start -0.35 -2.8) (end -2.35 -0.8) (layer B.Fab) (width 0.1))
(fp_line (start 9.85 -2.8) (end -0.35 -2.8) (layer B.Fab) (width 0.1))
(fp_line (start 9.85 7.2) (end 9.85 -2.8) (layer B.Fab) (width 0.1))
(fp_line (start -2.35 7.2) (end 9.85 7.2) (layer B.Fab) (width 0.1))
(fp_text user %R (at 3.75 2.2) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(pad 4 thru_hole oval (at 7.5 5) (size 1.8 3) (drill 1.2) (layers *.Cu *.Mask)
(net 23 V_LED))
(pad 4 thru_hole oval (at 7.5 0) (size 1.8 3) (drill 1.2) (layers *.Cu *.Mask)
(net 23 V_LED))
(pad 3 thru_hole oval (at 5 5) (size 1.8 3) (drill 1.2) (layers *.Cu *.Mask)
(net 1 -15V))
(pad 3 thru_hole oval (at 5 0) (size 1.8 3) (drill 1.2) (layers *.Cu *.Mask)
(net 1 -15V))
(pad 2 thru_hole oval (at 2.5 5) (size 1.8 3) (drill 1.2) (layers *.Cu *.Mask)
(net 2 +15V))
(pad 2 thru_hole oval (at 2.5 0) (size 1.8 3) (drill 1.2) (layers *.Cu *.Mask)
(net 2 +15V))
(pad 1 thru_hole rect (at 0 5) (size 1.8 3) (drill 1.2) (layers *.Cu *.Mask)
(net 3 GND))
(pad 1 thru_hole rect (at 0 0) (size 1.8 3) (drill 1.2) (layers *.Cu *.Mask)
(net 3 GND))
(model ${KISYS3DMOD}/TerminalBlock_Phoenix.3dshapes/TerminalBlock_Phoenix_PTSM-0,5-4-2.5-H-THR_1x04_P2.50mm_Horizontal.wrl
Schematic Main: Add corrected headphone amp
2020-11-09 22:22:35 +00:00
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(module TerminalBlock_Phoenix:TerminalBlock_Phoenix_PTSM-0,5-2-2.5-H-THR_1x02_P2.50mm_Horizontal (layer B.Cu) (tedit 5B294EBC) (tstamp 60B1C57D)
(at 53.34 107.95 90)
(descr "Terminal Block Phoenix PTSM-0,5-2-2.5-H-THR, 2 pins, pitch 2.5mm, size 7.2x10mm^2, drill diamater 1.2mm, pad diameter 3mm, see http://www.produktinfo.conrad.com/datenblaetter/550000-574999/556441-da-01-de-LEITERPLATTENKL__PTSM_0_5__8_2_5_H_THR.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix")
(tags "THT Terminal Block Phoenix PTSM-0,5-2-2.5-H-THR pitch 2.5mm size 7.2x10mm^2 drill 1.2mm pad 3mm")
(path /60B4299F)
(fp_text reference J105 (at 1.25 8.26 90) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value Output (at 1.25 -3.86 90) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_line (start 5.35 7.7) (end -2.85 7.7) (layer B.CrtYd) (width 0.05))
(fp_line (start 5.35 -3.3) (end 5.35 7.7) (layer B.CrtYd) (width 0.05))
(fp_line (start -2.85 -3.3) (end 5.35 -3.3) (layer B.CrtYd) (width 0.05))
(fp_line (start -2.85 7.7) (end -2.85 -3.3) (layer B.CrtYd) (width 0.05))
(fp_line (start -2.65 -3.1) (end -0.65 -3.1) (layer B.SilkS) (width 0.12))
(fp_line (start -2.65 -0.86) (end -2.65 -3.1) (layer B.SilkS) (width 0.12))
(fp_line (start 4.91 7.26) (end 4.91 -2.86) (layer B.SilkS) (width 0.12))
(fp_line (start -2.41 7.26) (end -2.41 -2.86) (layer B.SilkS) (width 0.12))
(fp_line (start -2.41 -2.86) (end 4.91 -2.86) (layer B.SilkS) (width 0.12))
(fp_line (start -2.41 7.26) (end 4.91 7.26) (layer B.SilkS) (width 0.12))
(fp_line (start -2.35 -0.8) (end -2.35 7.2) (layer B.Fab) (width 0.1))
(fp_line (start -0.35 -2.8) (end -2.35 -0.8) (layer B.Fab) (width 0.1))
(fp_line (start 4.85 -2.8) (end -0.35 -2.8) (layer B.Fab) (width 0.1))
(fp_line (start 4.85 7.2) (end 4.85 -2.8) (layer B.Fab) (width 0.1))
(fp_line (start -2.35 7.2) (end 4.85 7.2) (layer B.Fab) (width 0.1))
(fp_text user %R (at 1.25 2.2 90) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(pad 2 thru_hole oval (at 2.5 5 90) (size 1.8 3) (drill 1.2) (layers *.Cu *.Mask)
(net 75 /PreampOut))
(pad 2 thru_hole oval (at 2.5 0 90) (size 1.8 3) (drill 1.2) (layers *.Cu *.Mask)
(net 75 /PreampOut))
(pad 1 thru_hole rect (at 0 5 90) (size 1.8 3) (drill 1.2) (layers *.Cu *.Mask)
(net 3 GND))
(pad 1 thru_hole rect (at 0 0 90) (size 1.8 3) (drill 1.2) (layers *.Cu *.Mask)
(net 3 GND))
(model ${KISYS3DMOD}/TerminalBlock_Phoenix.3dshapes/TerminalBlock_Phoenix_PTSM-0,5-2-2.5-H-THR_1x02_P2.50mm_Horizontal.wrl
Main: Summing design flaw fixed; better headphone vol. range - Multiple R and C value adaptions - Line Input: No relevant difference between INA134 and own circuit -> LM833 chosen - Signal busses/ summing module inputs fixed - TODO: On-Air Button - TODO: Update PCB layout
2020-12-13 21:02:02 +00:00
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(module TerminalBlock_Phoenix:TerminalBlock_Phoenix_PTSM-0,5-4-2.5-H-THR_1x04_P2.50mm_Horizontal (layer B.Cu) (tedit 5B294EBC) (tstamp 60B1C567)
(at 53.34 151.13 90)
(descr "Terminal Block Phoenix PTSM-0,5-4-2.5-H-THR, 4 pins, pitch 2.5mm, size 12.2x10mm^2, drill diamater 1.2mm, pad diameter 3mm, see http://www.produktinfo.conrad.com/datenblaetter/550000-574999/556441-da-01-de-LEITERPLATTENKL__PTSM_0_5__8_2_5_H_THR.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix")
(tags "THT Terminal Block Phoenix PTSM-0,5-4-2.5-H-THR pitch 2.5mm size 12.2x10mm^2 drill 1.2mm pad 3mm")
(path /60C80007)
(fp_text reference J104 (at 3.75 8.26 90) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value Inputs (at 3.75 -3.86 90) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_line (start 10.35 7.7) (end -2.85 7.7) (layer B.CrtYd) (width 0.05))
(fp_line (start 10.35 -3.3) (end 10.35 7.7) (layer B.CrtYd) (width 0.05))
(fp_line (start -2.85 -3.3) (end 10.35 -3.3) (layer B.CrtYd) (width 0.05))
(fp_line (start -2.85 7.7) (end -2.85 -3.3) (layer B.CrtYd) (width 0.05))
(fp_line (start -2.65 -3.1) (end -0.65 -3.1) (layer B.SilkS) (width 0.12))
(fp_line (start -2.65 -0.86) (end -2.65 -3.1) (layer B.SilkS) (width 0.12))
(fp_line (start 9.91 7.26) (end 9.91 -2.86) (layer B.SilkS) (width 0.12))
(fp_line (start -2.41 7.26) (end -2.41 -2.86) (layer B.SilkS) (width 0.12))
(fp_line (start -2.41 -2.86) (end 9.91 -2.86) (layer B.SilkS) (width 0.12))
(fp_line (start -2.41 7.26) (end 9.91 7.26) (layer B.SilkS) (width 0.12))
(fp_line (start -2.35 -0.8) (end -2.35 7.2) (layer B.Fab) (width 0.1))
(fp_line (start -0.35 -2.8) (end -2.35 -0.8) (layer B.Fab) (width 0.1))
(fp_line (start 9.85 -2.8) (end -0.35 -2.8) (layer B.Fab) (width 0.1))
(fp_line (start 9.85 7.2) (end 9.85 -2.8) (layer B.Fab) (width 0.1))
(fp_line (start -2.35 7.2) (end 9.85 7.2) (layer B.Fab) (width 0.1))
(fp_text user %R (at 3.75 2.2 90) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(pad 4 thru_hole oval (at 7.5 5 90) (size 1.8 3) (drill 1.2) (layers *.Cu *.Mask)
(net 39 /Monitor_OthersB))
(pad 4 thru_hole oval (at 7.5 0 90) (size 1.8 3) (drill 1.2) (layers *.Cu *.Mask)
(net 39 /Monitor_OthersB))
(pad 3 thru_hole oval (at 5 5 90) (size 1.8 3) (drill 1.2) (layers *.Cu *.Mask)
(net 40 /Monitor_OthersA))
(pad 3 thru_hole oval (at 5 0 90) (size 1.8 3) (drill 1.2) (layers *.Cu *.Mask)
(net 40 /Monitor_OthersA))
(pad 2 thru_hole oval (at 2.5 5 90) (size 1.8 3) (drill 1.2) (layers *.Cu *.Mask)
(net 41 /Monitor_Stage))
(pad 2 thru_hole oval (at 2.5 0 90) (size 1.8 3) (drill 1.2) (layers *.Cu *.Mask)
(net 41 /Monitor_Stage))
(pad 1 thru_hole rect (at 0 5 90) (size 1.8 3) (drill 1.2) (layers *.Cu *.Mask)
(net 3 GND))
(pad 1 thru_hole rect (at 0 0 90) (size 1.8 3) (drill 1.2) (layers *.Cu *.Mask)
(net 3 GND))
(model ${KISYS3DMOD}/TerminalBlock_Phoenix.3dshapes/TerminalBlock_Phoenix_PTSM-0,5-4-2.5-H-THR_1x04_P2.50mm_Horizontal.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module MountingHole:MountingHole_3.2mm_M3 (layer F.Cu) (tedit 56D1B4CB) (tstamp 60B6F3EF)
(at 122 167)
(descr "Mounting Hole 3.2mm, no annular, M3")
(tags "mounting hole 3.2mm no annular m3")
(path /613C942A)
(attr virtual)
(fp_text reference H303 (at 0 -4.2) (layer F.SilkS) hide
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(fp_text value MountingHole (at 0 4.2) (layer F.Fab)
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(fp_circle (center 0 0) (end 3.45 0) (layer F.CrtYd) (width 0.05))
(fp_circle (center 0 0) (end 3.2 0) (layer Cmts.User) (width 0.15))
(fp_text user %R (at 0.3 0) (layer F.Fab)
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(pad 1 np_thru_hole circle (at 0 0) (size 3.2 3.2) (drill 3.2) (layers *.Cu *.Mask))
)
(module MountingHole:MountingHole_3.2mm_M3 (layer F.Cu) (tedit 56D1B4CB) (tstamp 60B6F3E7)
(at 53 167)
(descr "Mounting Hole 3.2mm, no annular, M3")
(tags "mounting hole 3.2mm no annular m3")
(path /612A42CA)
(attr virtual)
(fp_text reference H302 (at 0 -4.2) (layer F.SilkS) hide
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value MountingHole (at 0 4.2) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_circle (center 0 0) (end 3.45 0) (layer F.CrtYd) (width 0.05))
(fp_circle (center 0 0) (end 3.2 0) (layer Cmts.User) (width 0.15))
(fp_text user %R (at 0.3 0) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(pad 1 np_thru_hole circle (at 0 0) (size 3.2 3.2) (drill 3.2) (layers *.Cu *.Mask))
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(module MountingHole:MountingHole_3.2mm_M3 (layer F.Cu) (tedit 56D1B4CB) (tstamp 60B6F3DF)
(at 53 53)
(descr "Mounting Hole 3.2mm, no annular, M3")
(tags "mounting hole 3.2mm no annular m3")
(path /61277394)
(attr virtual)
(fp_text reference H301 (at 0 -4.2) (layer F.Fab) hide
Main: Summing design flaw fixed; better headphone vol. range - Multiple R and C value adaptions - Line Input: No relevant difference between INA134 and own circuit -> LM833 chosen - Signal busses/ summing module inputs fixed - TODO: On-Air Button - TODO: Update PCB layout
2020-12-13 21:02:02 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(fp_text value MountingHole (at 0 4.2) (layer F.Fab)
Main: Summing design flaw fixed; better headphone vol. range - Multiple R and C value adaptions - Line Input: No relevant difference between INA134 and own circuit -> LM833 chosen - Signal busses/ summing module inputs fixed - TODO: On-Air Button - TODO: Update PCB layout
2020-12-13 21:02:02 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(fp_circle (center 0 0) (end 3.45 0) (layer F.CrtYd) (width 0.05))
(fp_circle (center 0 0) (end 3.2 0) (layer Cmts.User) (width 0.15))
(fp_text user %R (at 0.3 0) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 1 np_thru_hole circle (at 0 0) (size 3.2 3.2) (drill 3.2) (layers *.Cu *.Mask))
)
(module Diode_THT:D_DO-35_SOD27_P10.16mm_Horizontal (layer F.Cu) (tedit 5AE50CD5) (tstamp 60B1C4B4)
(at 97.79 133.35)
(descr "Diode, DO-35_SOD27 series, Axial, Horizontal, pin pitch=10.16mm, , length*diameter=4*2mm^2, , http://www.diodes.com/_files/packages/DO-35.pdf")
(tags "Diode DO-35_SOD27 series Axial Horizontal pin pitch 10.16mm length 4mm diameter 2mm")
(path /60B42955)
(fp_text reference D119 (at 5.08 -2.12) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 1N4148 (at 5.08 2.12) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 3.08 -1) (end 3.08 1) (layer F.Fab) (width 0.1))
(fp_line (start 3.08 1) (end 7.08 1) (layer F.Fab) (width 0.1))
(fp_line (start 7.08 1) (end 7.08 -1) (layer F.Fab) (width 0.1))
(fp_line (start 7.08 -1) (end 3.08 -1) (layer F.Fab) (width 0.1))
(fp_line (start 0 0) (end 3.08 0) (layer F.Fab) (width 0.1))
(fp_line (start 10.16 0) (end 7.08 0) (layer F.Fab) (width 0.1))
(fp_line (start 3.68 -1) (end 3.68 1) (layer F.Fab) (width 0.1))
(fp_line (start 3.78 -1) (end 3.78 1) (layer F.Fab) (width 0.1))
(fp_line (start 3.58 -1) (end 3.58 1) (layer F.Fab) (width 0.1))
(fp_line (start 2.96 -1.12) (end 2.96 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 2.96 1.12) (end 7.2 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 7.2 1.12) (end 7.2 -1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 7.2 -1.12) (end 2.96 -1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 1.04 0) (end 2.96 0) (layer F.SilkS) (width 0.12))
(fp_line (start 9.12 0) (end 7.2 0) (layer F.SilkS) (width 0.12))
(fp_line (start 3.68 -1.12) (end 3.68 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 3.8 -1.12) (end 3.8 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 3.56 -1.12) (end 3.56 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start -1.05 -1.25) (end -1.05 1.25) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.25) (end 11.21 1.25) (layer F.CrtYd) (width 0.05))
(fp_line (start 11.21 1.25) (end 11.21 -1.25) (layer F.CrtYd) (width 0.05))
(fp_line (start 11.21 -1.25) (end -1.05 -1.25) (layer F.CrtYd) (width 0.05))
(fp_text user K (at 0 -1.8) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user K (at 0 -1.8) (layer F.Fab)
Main: Summing design flaw fixed; better headphone vol. range - Multiple R and C value adaptions - Line Input: No relevant difference between INA134 and own circuit -> LM833 chosen - Signal busses/ summing module inputs fixed - TODO: On-Air Button - TODO: Update PCB layout
2020-12-13 21:02:02 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(fp_text user %R (at 5.38 0) (layer F.Fab)
(effects (font (size 0.8 0.8) (thickness 0.12)))
)
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
(pad 2 thru_hole oval (at 10.16 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(net 37 "Net-(D118-Pad1)"))
(pad 1 thru_hole rect (at 0 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 20 "Net-(C120-Pad1)"))
(model ${KISYS3DMOD}/Diode_THT.3dshapes/D_DO-35_SOD27_P10.16mm_Horizontal.wrl
Main: Summing design flaw fixed; better headphone vol. range - Multiple R and C value adaptions - Line Input: No relevant difference between INA134 and own circuit -> LM833 chosen - Signal busses/ summing module inputs fixed - TODO: On-Air Button - TODO: Update PCB layout
2020-12-13 21:02:02 +00:00
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(module Package_DIP:DIP-8_W7.62mm_Socket_LongPads (layer B.Cu) (tedit 5A02E8C5) (tstamp 60B1CBD9)
(at 123.19 140.97 180)
(descr "8-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), Socket, LongPads")
(tags "THT DIP DIL PDIP 2.54mm 7.62mm 300mil Socket LongPads")
(path /60B42934)
(fp_text reference U104 (at 3.81 2.33) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value LM833N (at 3.81 -9.95) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_line (start 1.635 1.27) (end 6.985 1.27) (layer B.Fab) (width 0.1))
(fp_line (start 6.985 1.27) (end 6.985 -8.89) (layer B.Fab) (width 0.1))
(fp_line (start 6.985 -8.89) (end 0.635 -8.89) (layer B.Fab) (width 0.1))
(fp_line (start 0.635 -8.89) (end 0.635 0.27) (layer B.Fab) (width 0.1))
(fp_line (start 0.635 0.27) (end 1.635 1.27) (layer B.Fab) (width 0.1))
(fp_line (start -1.27 1.33) (end -1.27 -8.95) (layer B.Fab) (width 0.1))
(fp_line (start -1.27 -8.95) (end 8.89 -8.95) (layer B.Fab) (width 0.1))
(fp_line (start 8.89 -8.95) (end 8.89 1.33) (layer B.Fab) (width 0.1))
(fp_line (start 8.89 1.33) (end -1.27 1.33) (layer B.Fab) (width 0.1))
(fp_line (start 2.81 1.33) (end 1.56 1.33) (layer B.SilkS) (width 0.12))
(fp_line (start 1.56 1.33) (end 1.56 -8.95) (layer B.SilkS) (width 0.12))
(fp_line (start 1.56 -8.95) (end 6.06 -8.95) (layer B.SilkS) (width 0.12))
(fp_line (start 6.06 -8.95) (end 6.06 1.33) (layer B.SilkS) (width 0.12))
(fp_line (start 6.06 1.33) (end 4.81 1.33) (layer B.SilkS) (width 0.12))
(fp_line (start -1.44 1.39) (end -1.44 -9.01) (layer B.SilkS) (width 0.12))
(fp_line (start -1.44 -9.01) (end 9.06 -9.01) (layer B.SilkS) (width 0.12))
(fp_line (start 9.06 -9.01) (end 9.06 1.39) (layer B.SilkS) (width 0.12))
(fp_line (start 9.06 1.39) (end -1.44 1.39) (layer B.SilkS) (width 0.12))
(fp_line (start -1.55 1.6) (end -1.55 -9.2) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.55 -9.2) (end 9.15 -9.2) (layer B.CrtYd) (width 0.05))
(fp_line (start 9.15 -9.2) (end 9.15 1.6) (layer B.CrtYd) (width 0.05))
(fp_line (start 9.15 1.6) (end -1.55 1.6) (layer B.CrtYd) (width 0.05))
(fp_text user %R (at 3.81 -3.81) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_arc (start 3.81 1.33) (end 2.81 1.33) (angle 180) (layer B.SilkS) (width 0.12))
(pad 8 thru_hole oval (at 7.62 0 180) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 2 +15V))
(pad 4 thru_hole oval (at 0 -7.62 180) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 1 -15V))
(pad 7 thru_hole oval (at 7.62 -2.54 180) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 37 "Net-(D118-Pad1)"))
(pad 3 thru_hole oval (at 0 -5.08 180) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask))
(pad 6 thru_hole oval (at 7.62 -5.08 180) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 36 "Net-(D118-Pad2)"))
(pad 2 thru_hole oval (at 0 -2.54 180) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask))
(pad 5 thru_hole oval (at 7.62 -7.62 180) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 3 GND))
(pad 1 thru_hole rect (at 0 0 180) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask))
(model ${KISYS3DMOD}/Package_DIP.3dshapes/DIP-8_W7.62mm_Socket.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
Main: Summing design flaw fixed; better headphone vol. range - Multiple R and C value adaptions - Line Input: No relevant difference between INA134 and own circuit -> LM833 chosen - Signal busses/ summing module inputs fixed - TODO: On-Air Button - TODO: Update PCB layout
2020-12-13 21:02:02 +00:00
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
)
(module Package_DIP:DIP-14_W7.62mm_Socket_LongPads (layer B.Cu) (tedit 5A02E8C5) (tstamp 60B1CBB5)
(at 101.6 71.12)
(descr "14-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), Socket, LongPads")
(tags "THT DIP DIL PDIP 2.54mm 7.62mm 300mil Socket LongPads")
(path /60B4290D)
(fp_text reference U107 (at 3.81 2.33) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value LM339 (at 3.81 -17.57) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_line (start 1.635 1.27) (end 6.985 1.27) (layer B.Fab) (width 0.1))
(fp_line (start 6.985 1.27) (end 6.985 -16.51) (layer B.Fab) (width 0.1))
(fp_line (start 6.985 -16.51) (end 0.635 -16.51) (layer B.Fab) (width 0.1))
(fp_line (start 0.635 -16.51) (end 0.635 0.27) (layer B.Fab) (width 0.1))
(fp_line (start 0.635 0.27) (end 1.635 1.27) (layer B.Fab) (width 0.1))
(fp_line (start -1.27 1.33) (end -1.27 -16.57) (layer B.Fab) (width 0.1))
(fp_line (start -1.27 -16.57) (end 8.89 -16.57) (layer B.Fab) (width 0.1))
(fp_line (start 8.89 -16.57) (end 8.89 1.33) (layer B.Fab) (width 0.1))
(fp_line (start 8.89 1.33) (end -1.27 1.33) (layer B.Fab) (width 0.1))
(fp_line (start 2.81 1.33) (end 1.56 1.33) (layer B.SilkS) (width 0.12))
(fp_line (start 1.56 1.33) (end 1.56 -16.57) (layer B.SilkS) (width 0.12))
(fp_line (start 1.56 -16.57) (end 6.06 -16.57) (layer B.SilkS) (width 0.12))
(fp_line (start 6.06 -16.57) (end 6.06 1.33) (layer B.SilkS) (width 0.12))
(fp_line (start 6.06 1.33) (end 4.81 1.33) (layer B.SilkS) (width 0.12))
(fp_line (start -1.44 1.39) (end -1.44 -16.63) (layer B.SilkS) (width 0.12))
(fp_line (start -1.44 -16.63) (end 9.06 -16.63) (layer B.SilkS) (width 0.12))
(fp_line (start 9.06 -16.63) (end 9.06 1.39) (layer B.SilkS) (width 0.12))
(fp_line (start 9.06 1.39) (end -1.44 1.39) (layer B.SilkS) (width 0.12))
(fp_line (start -1.55 1.6) (end -1.55 -16.85) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.55 -16.85) (end 9.15 -16.85) (layer B.CrtYd) (width 0.05))
(fp_line (start 9.15 -16.85) (end 9.15 1.6) (layer B.CrtYd) (width 0.05))
(fp_line (start 9.15 1.6) (end -1.55 1.6) (layer B.CrtYd) (width 0.05))
(fp_text user %R (at 3.81 -7.62) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_arc (start 3.81 1.33) (end 2.81 1.33) (angle 180) (layer B.SilkS) (width 0.12))
(pad 14 thru_hole oval (at 7.62 0) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 59 "Net-(R129-Pad2)"))
(pad 7 thru_hole oval (at 0 -15.24) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 73 "Net-(R144-Pad2)"))
(pad 13 thru_hole oval (at 7.62 -2.54) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 60 "Net-(R130-Pad2)"))
(pad 6 thru_hole oval (at 0 -12.7) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 20 "Net-(C120-Pad1)"))
(pad 12 thru_hole oval (at 7.62 -5.08) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 3 GND))
(pad 5 thru_hole oval (at 0 -10.16) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 74 "Net-(R145-Pad2)"))
(pad 11 thru_hole oval (at 7.62 -7.62) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 72 "Net-(R143-Pad2)"))
(pad 4 thru_hole oval (at 0 -7.62) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 20 "Net-(C120-Pad1)"))
(pad 10 thru_hole oval (at 7.62 -10.16) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 20 "Net-(C120-Pad1)"))
(pad 3 thru_hole oval (at 0 -5.08) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 2 +15V))
(pad 9 thru_hole oval (at 7.62 -12.7) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 71 "Net-(R142-Pad2)"))
(pad 2 thru_hole oval (at 0 -2.54) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 62 "Net-(R132-Pad2)"))
(pad 8 thru_hole oval (at 7.62 -15.24) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 20 "Net-(C120-Pad1)"))
(pad 1 thru_hole rect (at 0 0) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 61 "Net-(R131-Pad2)"))
(model ${KISYS3DMOD}/Package_DIP.3dshapes/DIP-14_W7.62mm_Socket.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
Main: Summing design flaw fixed; better headphone vol. range - Multiple R and C value adaptions - Line Input: No relevant difference between INA134 and own circuit -> LM833 chosen - Signal busses/ summing module inputs fixed - TODO: On-Air Button - TODO: Update PCB layout
2020-12-13 21:02:02 +00:00
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
)
(module Package_DIP:DIP-14_W7.62mm_Socket_LongPads (layer B.Cu) (tedit 5A02E8C5) (tstamp 60B1CB8B)
(at 101.6 96.52)
(descr "14-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), Socket, LongPads")
(tags "THT DIP DIL PDIP 2.54mm 7.62mm 300mil Socket LongPads")
(path /60B42907)
(fp_text reference U106 (at 3.81 2.33) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value LM339 (at 3.81 -17.57) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_line (start 1.635 1.27) (end 6.985 1.27) (layer B.Fab) (width 0.1))
(fp_line (start 6.985 1.27) (end 6.985 -16.51) (layer B.Fab) (width 0.1))
(fp_line (start 6.985 -16.51) (end 0.635 -16.51) (layer B.Fab) (width 0.1))
(fp_line (start 0.635 -16.51) (end 0.635 0.27) (layer B.Fab) (width 0.1))
(fp_line (start 0.635 0.27) (end 1.635 1.27) (layer B.Fab) (width 0.1))
(fp_line (start -1.27 1.33) (end -1.27 -16.57) (layer B.Fab) (width 0.1))
(fp_line (start -1.27 -16.57) (end 8.89 -16.57) (layer B.Fab) (width 0.1))
(fp_line (start 8.89 -16.57) (end 8.89 1.33) (layer B.Fab) (width 0.1))
(fp_line (start 8.89 1.33) (end -1.27 1.33) (layer B.Fab) (width 0.1))
(fp_line (start 2.81 1.33) (end 1.56 1.33) (layer B.SilkS) (width 0.12))
(fp_line (start 1.56 1.33) (end 1.56 -16.57) (layer B.SilkS) (width 0.12))
(fp_line (start 1.56 -16.57) (end 6.06 -16.57) (layer B.SilkS) (width 0.12))
(fp_line (start 6.06 -16.57) (end 6.06 1.33) (layer B.SilkS) (width 0.12))
(fp_line (start 6.06 1.33) (end 4.81 1.33) (layer B.SilkS) (width 0.12))
(fp_line (start -1.44 1.39) (end -1.44 -16.63) (layer B.SilkS) (width 0.12))
(fp_line (start -1.44 -16.63) (end 9.06 -16.63) (layer B.SilkS) (width 0.12))
(fp_line (start 9.06 -16.63) (end 9.06 1.39) (layer B.SilkS) (width 0.12))
(fp_line (start 9.06 1.39) (end -1.44 1.39) (layer B.SilkS) (width 0.12))
(fp_line (start -1.55 1.6) (end -1.55 -16.85) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.55 -16.85) (end 9.15 -16.85) (layer B.CrtYd) (width 0.05))
(fp_line (start 9.15 -16.85) (end 9.15 1.6) (layer B.CrtYd) (width 0.05))
(fp_line (start 9.15 1.6) (end -1.55 1.6) (layer B.CrtYd) (width 0.05))
(fp_text user %R (at 3.81 -7.62) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_arc (start 3.81 1.33) (end 2.81 1.33) (angle 180) (layer B.SilkS) (width 0.12))
(pad 14 thru_hole oval (at 7.62 0) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 55 "Net-(R125-Pad2)"))
(pad 7 thru_hole oval (at 0 -15.24) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 69 "Net-(R140-Pad2)"))
(pad 13 thru_hole oval (at 7.62 -2.54) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 56 "Net-(R126-Pad2)"))
(pad 6 thru_hole oval (at 0 -12.7) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 20 "Net-(C120-Pad1)"))
(pad 12 thru_hole oval (at 7.62 -5.08) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 3 GND))
(pad 5 thru_hole oval (at 0 -10.16) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 70 "Net-(R141-Pad2)"))
(pad 11 thru_hole oval (at 7.62 -7.62) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 68 "Net-(R139-Pad2)"))
(pad 4 thru_hole oval (at 0 -7.62) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 20 "Net-(C120-Pad1)"))
(pad 10 thru_hole oval (at 7.62 -10.16) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 20 "Net-(C120-Pad1)"))
(pad 3 thru_hole oval (at 0 -5.08) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 2 +15V))
(pad 9 thru_hole oval (at 7.62 -12.7) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 67 "Net-(R138-Pad2)"))
(pad 2 thru_hole oval (at 0 -2.54) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 58 "Net-(R128-Pad2)"))
(pad 8 thru_hole oval (at 7.62 -15.24) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 20 "Net-(C120-Pad1)"))
(pad 1 thru_hole rect (at 0 0) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 57 "Net-(R127-Pad2)"))
(model ${KISYS3DMOD}/Package_DIP.3dshapes/DIP-14_W7.62mm_Socket.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
Main: Summing design flaw fixed; better headphone vol. range - Multiple R and C value adaptions - Line Input: No relevant difference between INA134 and own circuit -> LM833 chosen - Signal busses/ summing module inputs fixed - TODO: On-Air Button - TODO: Update PCB layout
2020-12-13 21:02:02 +00:00
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
)
(module Package_DIP:DIP-14_W7.62mm_Socket_LongPads (layer B.Cu) (tedit 5A02E8C5) (tstamp 60B1CB61)
(at 101.6 121.92)
(descr "14-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), Socket, LongPads")
(tags "THT DIP DIL PDIP 2.54mm 7.62mm 300mil Socket LongPads")
(path /60B42758)
(fp_text reference U105 (at 3.81 2.33) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value LM339 (at 3.81 -17.57) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_line (start 1.635 1.27) (end 6.985 1.27) (layer B.Fab) (width 0.1))
(fp_line (start 6.985 1.27) (end 6.985 -16.51) (layer B.Fab) (width 0.1))
(fp_line (start 6.985 -16.51) (end 0.635 -16.51) (layer B.Fab) (width 0.1))
(fp_line (start 0.635 -16.51) (end 0.635 0.27) (layer B.Fab) (width 0.1))
(fp_line (start 0.635 0.27) (end 1.635 1.27) (layer B.Fab) (width 0.1))
(fp_line (start -1.27 1.33) (end -1.27 -16.57) (layer B.Fab) (width 0.1))
(fp_line (start -1.27 -16.57) (end 8.89 -16.57) (layer B.Fab) (width 0.1))
(fp_line (start 8.89 -16.57) (end 8.89 1.33) (layer B.Fab) (width 0.1))
(fp_line (start 8.89 1.33) (end -1.27 1.33) (layer B.Fab) (width 0.1))
(fp_line (start 2.81 1.33) (end 1.56 1.33) (layer B.SilkS) (width 0.12))
(fp_line (start 1.56 1.33) (end 1.56 -16.57) (layer B.SilkS) (width 0.12))
(fp_line (start 1.56 -16.57) (end 6.06 -16.57) (layer B.SilkS) (width 0.12))
(fp_line (start 6.06 -16.57) (end 6.06 1.33) (layer B.SilkS) (width 0.12))
(fp_line (start 6.06 1.33) (end 4.81 1.33) (layer B.SilkS) (width 0.12))
(fp_line (start -1.44 1.39) (end -1.44 -16.63) (layer B.SilkS) (width 0.12))
(fp_line (start -1.44 -16.63) (end 9.06 -16.63) (layer B.SilkS) (width 0.12))
(fp_line (start 9.06 -16.63) (end 9.06 1.39) (layer B.SilkS) (width 0.12))
(fp_line (start 9.06 1.39) (end -1.44 1.39) (layer B.SilkS) (width 0.12))
(fp_line (start -1.55 1.6) (end -1.55 -16.85) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.55 -16.85) (end 9.15 -16.85) (layer B.CrtYd) (width 0.05))
(fp_line (start 9.15 -16.85) (end 9.15 1.6) (layer B.CrtYd) (width 0.05))
(fp_line (start 9.15 1.6) (end -1.55 1.6) (layer B.CrtYd) (width 0.05))
(fp_text user %R (at 3.81 -7.62) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_arc (start 3.81 1.33) (end 2.81 1.33) (angle 180) (layer B.SilkS) (width 0.12))
(pad 14 thru_hole oval (at 7.62 0) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 51 "Net-(R121-Pad2)"))
(pad 7 thru_hole oval (at 0 -15.24) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 65 "Net-(R136-Pad2)"))
(pad 13 thru_hole oval (at 7.62 -2.54) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 52 "Net-(R122-Pad2)"))
(pad 6 thru_hole oval (at 0 -12.7) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 20 "Net-(C120-Pad1)"))
(pad 12 thru_hole oval (at 7.62 -5.08) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 3 GND))
(pad 5 thru_hole oval (at 0 -10.16) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 66 "Net-(R137-Pad2)"))
(pad 11 thru_hole oval (at 7.62 -7.62) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 64 "Net-(R135-Pad2)"))
(pad 4 thru_hole oval (at 0 -7.62) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 20 "Net-(C120-Pad1)"))
(pad 10 thru_hole oval (at 7.62 -10.16) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 20 "Net-(C120-Pad1)"))
(pad 3 thru_hole oval (at 0 -5.08) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 2 +15V))
(pad 9 thru_hole oval (at 7.62 -12.7) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 63 "Net-(R134-Pad2)"))
(pad 2 thru_hole oval (at 0 -2.54) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 54 "Net-(R124-Pad2)"))
(pad 8 thru_hole oval (at 7.62 -15.24) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 20 "Net-(C120-Pad1)"))
(pad 1 thru_hole rect (at 0 0) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 53 "Net-(R123-Pad2)"))
(model ${KISYS3DMOD}/Package_DIP.3dshapes/DIP-14_W7.62mm_Socket.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Package_DIP:DIP-8_W7.62mm_Socket_LongPads (layer B.Cu) (tedit 5A02E8C5) (tstamp 60B1CB14)
(at 60.96 119.38 270)
(descr "8-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), Socket, LongPads")
(tags "THT DIP DIL PDIP 2.54mm 7.62mm 300mil Socket LongPads")
(path /5FFF673D)
(fp_text reference U102 (at 3.81 2.33 270) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value LM833N (at 3.81 -9.95 270) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_line (start 1.635 1.27) (end 6.985 1.27) (layer B.Fab) (width 0.1))
(fp_line (start 6.985 1.27) (end 6.985 -8.89) (layer B.Fab) (width 0.1))
(fp_line (start 6.985 -8.89) (end 0.635 -8.89) (layer B.Fab) (width 0.1))
(fp_line (start 0.635 -8.89) (end 0.635 0.27) (layer B.Fab) (width 0.1))
(fp_line (start 0.635 0.27) (end 1.635 1.27) (layer B.Fab) (width 0.1))
(fp_line (start -1.27 1.33) (end -1.27 -8.95) (layer B.Fab) (width 0.1))
(fp_line (start -1.27 -8.95) (end 8.89 -8.95) (layer B.Fab) (width 0.1))
(fp_line (start 8.89 -8.95) (end 8.89 1.33) (layer B.Fab) (width 0.1))
(fp_line (start 8.89 1.33) (end -1.27 1.33) (layer B.Fab) (width 0.1))
(fp_line (start 2.81 1.33) (end 1.56 1.33) (layer B.SilkS) (width 0.12))
(fp_line (start 1.56 1.33) (end 1.56 -8.95) (layer B.SilkS) (width 0.12))
(fp_line (start 1.56 -8.95) (end 6.06 -8.95) (layer B.SilkS) (width 0.12))
(fp_line (start 6.06 -8.95) (end 6.06 1.33) (layer B.SilkS) (width 0.12))
(fp_line (start 6.06 1.33) (end 4.81 1.33) (layer B.SilkS) (width 0.12))
(fp_line (start -1.44 1.39) (end -1.44 -9.01) (layer B.SilkS) (width 0.12))
(fp_line (start -1.44 -9.01) (end 9.06 -9.01) (layer B.SilkS) (width 0.12))
(fp_line (start 9.06 -9.01) (end 9.06 1.39) (layer B.SilkS) (width 0.12))
(fp_line (start 9.06 1.39) (end -1.44 1.39) (layer B.SilkS) (width 0.12))
(fp_line (start -1.55 1.6) (end -1.55 -9.2) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.55 -9.2) (end 9.15 -9.2) (layer B.CrtYd) (width 0.05))
(fp_line (start 9.15 -9.2) (end 9.15 1.6) (layer B.CrtYd) (width 0.05))
(fp_line (start 9.15 1.6) (end -1.55 1.6) (layer B.CrtYd) (width 0.05))
(fp_text user %R (at 3.81 -3.81 270) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_arc (start 3.81 1.33) (end 2.81 1.33) (angle 180) (layer B.SilkS) (width 0.12))
(pad 8 thru_hole oval (at 7.62 0 270) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 2 +15V))
(pad 4 thru_hole oval (at 0 -7.62 270) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 1 -15V))
(pad 7 thru_hole oval (at 7.62 -2.54 270) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 76 SumOut))
(pad 3 thru_hole oval (at 0 -5.08 270) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 3 GND))
(pad 6 thru_hole oval (at 7.62 -5.08 270) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 4 "Net-(C103-Pad2)"))
(pad 2 thru_hole oval (at 0 -2.54 270) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 5 "Net-(C106-Pad2)"))
(pad 5 thru_hole oval (at 7.62 -7.62 270) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 3 GND))
(pad 1 thru_hole rect (at 0 0 270) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 75 /PreampOut))
(model ${KISYS3DMOD}/Package_DIP.3dshapes/DIP-8_W7.62mm_Socket.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module c3lingo_unit-footprints:SW_APEM_MHPS2273_DPDT locked (layer F.Cu) (tedit 60B14EA2) (tstamp 60B1CA7F)
(at 68 70 180)
(path /63519724)
(fp_text reference SW101 (at 0.3 4.5) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value OnAir_X (at 0.7 -5) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -3.6 3.6) (end -3.6 -3.6) (layer F.SilkS) (width 0.12))
(fp_line (start 3.6 3.6) (end -3.6 3.6) (layer F.SilkS) (width 0.12))
(fp_line (start 3.6 -3.6) (end 3.6 3.6) (layer F.SilkS) (width 0.12))
(fp_line (start -3.6 -3.6) (end 3.6 -3.6) (layer F.SilkS) (width 0.12))
(fp_line (start -5.8 -5.8) (end 5.8 -5.8) (layer F.CrtYd) (width 0.02))
(fp_line (start 5.8 -5.8) (end 5.8 5.8) (layer F.CrtYd) (width 0.02))
(fp_line (start 5.8 5.8) (end -5.8 5.8) (layer F.CrtYd) (width 0.02))
(fp_line (start -5.8 5.8) (end -5.8 -5.8) (layer F.CrtYd) (width 0.02))
(pad 6 thru_hole circle (at 2 2.5 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 21 "Net-(D101-Pad2)"))
(pad 5 thru_hole circle (at 0 2.5 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 23 V_LED))
(pad 4 thru_hole circle (at -2 2.5 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask))
(pad 3 thru_hole circle (at 2 -2.5 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask))
(pad 2 thru_hole circle (at 0 -2.5 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 5 "Net-(C106-Pad2)"))
(pad 1 thru_hole circle (at -2 -2.5 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 75 /PreampOut))
)
(module Potentiometer_THT:Potentiometer_Vishay_T73XX_Horizontal (layer B.Cu) (tedit 5A3D4993) (tstamp 60B1CA6D)
(at 105.41 148.59 270)
(descr "Potentiometer, horizontal, Vishay T73XX, http://www.vishay.com/docs/51016/t73.pdf")
(tags "Potentiometer horizontal Vishay T73XX")
(path /60B42964)
(fp_text reference RV106 (at 0 2.01 270) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value 50K (at 0 -7.09 270) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_line (start 3.68 0.76) (end 3.68 -5.84) (layer B.Fab) (width 0.1))
(fp_line (start 3.68 -5.84) (end -1.02 -5.84) (layer B.Fab) (width 0.1))
(fp_line (start -1.02 -5.84) (end -1.02 0.76) (layer B.Fab) (width 0.1))
(fp_line (start -1.02 0.76) (end 3.68 0.76) (layer B.Fab) (width 0.1))
(fp_line (start -1.14 0.88) (end -0.65 0.88) (layer B.SilkS) (width 0.12))
(fp_line (start 0.65 0.88) (end 3.8 0.88) (layer B.SilkS) (width 0.12))
(fp_line (start -1.14 -5.96) (end -0.65 -5.96) (layer B.SilkS) (width 0.12))
(fp_line (start 0.65 -5.96) (end 3.8 -5.96) (layer B.SilkS) (width 0.12))
(fp_line (start 3.8 0.88) (end 3.8 -5.96) (layer B.SilkS) (width 0.12))
(fp_line (start -1.14 0.88) (end -1.14 -5.96) (layer B.SilkS) (width 0.12))
(fp_line (start -1.3 1.05) (end -1.3 -6.1) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.3 -6.1) (end 3.95 -6.1) (layer B.CrtYd) (width 0.05))
(fp_line (start 3.95 -6.1) (end 3.95 1.05) (layer B.CrtYd) (width 0.05))
(fp_line (start 3.95 1.05) (end -1.3 1.05) (layer B.CrtYd) (width 0.05))
(fp_text user %R (at 1.33 -2.54 270) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(pad 1 thru_hole circle (at 0 0 270) (size 1.44 1.44) (drill 0.8) (layers *.Cu *.Mask)
(net 75 /PreampOut))
(pad 2 thru_hole circle (at 2.54 -2.54 270) (size 1.44 1.44) (drill 0.8) (layers *.Cu *.Mask)
(net 19 "Net-(C119-Pad1)"))
(pad 3 thru_hole circle (at 0 -5.08 270) (size 1.44 1.44) (drill 0.8) (layers *.Cu *.Mask)
(net 3 GND))
(model ${KISYS3DMOD}/Potentiometer_THT.3dshapes/Potentiometer_Vishay_T73XX_Horizontal.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module c3lingo_unit-footprints:Potentiometer_Alps_RK09K_Double_Vertical locked (layer F.Cu) (tedit 60B15712) (tstamp 5FAC7E76)
(at 109.5 165 90)
(descr "Potentiometer, vertical, Alps RK09L Double, http://www.alps.com/prod/info/E/HTML/Potentiometer/RotaryPotentiometers/RK09L/RK09L_list.html")
(tags "Potentiometer vertical Alps RK09L Double")
(path /5FD69197)
(fp_text reference RV105 (at 4.475 -10.5 90) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value "50K log. st." (at 4.475 5.5 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 12.6 -9.5) (end -3.65 -9.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 12.6 4.5) (end 12.6 -9.5) (layer F.CrtYd) (width 0.05))
(fp_line (start -3.65 4.5) (end 12.6 4.5) (layer F.CrtYd) (width 0.05))
(fp_line (start -3.65 -9.5) (end -3.65 4.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 12.47 -8.67) (end 12.47 3.67) (layer F.SilkS) (width 0.12))
(fp_line (start 0.88 0.87) (end 0.88 3.67) (layer F.SilkS) (width 0.12))
(fp_line (start 0.88 -1.629) (end 0.88 -0.87) (layer F.SilkS) (width 0.12))
(fp_line (start 0.88 -4.129) (end 0.88 -3.37) (layer F.SilkS) (width 0.12))
(fp_line (start 0.88 -8.67) (end 0.88 -5.871) (layer F.SilkS) (width 0.12))
(fp_line (start 9.455 3.67) (end 12.47 3.67) (layer F.SilkS) (width 0.12))
(fp_line (start 0.88 3.67) (end 5.546 3.67) (layer F.SilkS) (width 0.12))
(fp_line (start 9.455 -8.67) (end 12.47 -8.67) (layer F.SilkS) (width 0.12))
(fp_line (start 0.88 -8.67) (end 5.546 -8.67) (layer F.SilkS) (width 0.12))
(fp_line (start 12.35 -8.55) (end 1 -8.55) (layer F.Fab) (width 0.1))
(fp_line (start 12.35 3.55) (end 12.35 -8.55) (layer F.Fab) (width 0.1))
(fp_line (start 1 3.55) (end 12.35 3.55) (layer F.Fab) (width 0.1))
(fp_line (start 1 -8.55) (end 1 3.55) (layer F.Fab) (width 0.1))
(fp_circle (center 7.5 -2.5) (end 10.5 -2.5) (layer F.Fab) (width 0.1))
(fp_text user %R (at 2 -2.5) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 1 thru_hole circle (at 0 -5 180) (size 1.8 1.8) (drill 1) (layers *.Cu *.Mask)
(net 3 GND))
(pad 6 thru_hole circle (at 0 -2.5 90) (size 1.8 1.8) (drill 1) (layers *.Cu *.Mask)
(net 40 /Monitor_OthersA))
(pad 3 thru_hole circle (at 0 0 90) (size 1.8 1.8) (drill 1) (layers *.Cu *.Mask)
(net 39 /Monitor_OthersB))
(pad 5 thru_hole circle (at -2.5 -5 90) (size 1.8 1.8) (drill 1) (layers *.Cu *.Mask)
(net 48 "Net-(R117-Pad2)"))
(pad 2 thru_hole circle (at -2.5 0 90) (size 1.8 1.8) (drill 1) (layers *.Cu *.Mask)
(net 50 "Net-(R119-Pad2)"))
(pad "" np_thru_hole circle (at 7.5 -7.25 90) (size 4 4) (drill 2) (layers *.Cu *.Mask))
(pad "" np_thru_hole circle (at 7.5 2.25 90) (size 4 4) (drill 2) (layers *.Cu *.Mask))
(model ${KISYS3DMOD}/Potentiometer_THT.3dshapes/Potentiometer_Alps_RK09L_Double_Vertical.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Potentiometer_THT:Potentiometer_Alps_RK09K_Single_Horizontal locked (layer F.Cu) (tedit 5A3D4993) (tstamp 5FA9E264)
(at 111.5 229.5 270)
(descr "Potentiometer, horizontal, Alps RK09K Single, http://www.alps.com/prod/info/E/HTML/Potentiometer/RotaryPotentiometers/RK09K/RK09K_list.html")
(tags "Potentiometer horizontal Alps RK09K Single")
(path /5FBA2B4E)
(fp_text reference RV104 (at 0 -11.05 90) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value "50K log." (at 0 6.05 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -3.4 -7.4) (end -3.4 2.4) (layer F.Fab) (width 0.1))
(fp_line (start -3.4 2.4) (end 3.4 2.4) (layer F.Fab) (width 0.1))
(fp_line (start 3.4 2.4) (end 3.4 -7.4) (layer F.Fab) (width 0.1))
(fp_line (start 3.4 -7.4) (end -3.4 -7.4) (layer F.Fab) (width 0.1))
(fp_line (start 3.4 -5.75) (end 3.4 0.75) (layer F.Fab) (width 0.1))
(fp_line (start 3.4 0.75) (end 4.2 0.75) (layer F.Fab) (width 0.1))
(fp_line (start 4.2 0.75) (end 4.2 -5.75) (layer F.Fab) (width 0.1))
(fp_line (start 4.2 -5.75) (end 3.4 -5.75) (layer F.Fab) (width 0.1))
(fp_line (start 4.2 -5.5) (end 4.2 0.5) (layer F.Fab) (width 0.1))
(fp_line (start 4.2 0.5) (end 11.6 0.5) (layer F.Fab) (width 0.1))
(fp_line (start 11.6 0.5) (end 11.6 -5.5) (layer F.Fab) (width 0.1))
(fp_line (start 11.6 -5.5) (end 4.2 -5.5) (layer F.Fab) (width 0.1))
(fp_line (start -0.745 -7.521) (end 3.52 -7.521) (layer F.SilkS) (width 0.12))
(fp_line (start -0.745 2.52) (end 3.52 2.52) (layer F.SilkS) (width 0.12))
(fp_line (start -3.52 -4.944) (end -3.52 -0.055) (layer F.SilkS) (width 0.12))
(fp_line (start 3.52 -7.521) (end 3.52 2.52) (layer F.SilkS) (width 0.12))
(fp_line (start 3.52 -5.87) (end 4.32 -5.87) (layer F.SilkS) (width 0.12))
(fp_line (start 3.52 0.87) (end 4.32 0.87) (layer F.SilkS) (width 0.12))
(fp_line (start 3.52 -5.87) (end 3.52 0.87) (layer F.SilkS) (width 0.12))
(fp_line (start 4.32 -5.87) (end 4.32 0.87) (layer F.SilkS) (width 0.12))
(fp_line (start 4.32 -5.62) (end 11.72 -5.62) (layer F.SilkS) (width 0.12))
(fp_line (start 4.32 0.62) (end 11.72 0.62) (layer F.SilkS) (width 0.12))
(fp_line (start 4.32 -5.62) (end 4.32 0.62) (layer F.SilkS) (width 0.12))
(fp_line (start 11.72 -5.62) (end 11.72 0.62) (layer F.SilkS) (width 0.12))
(fp_line (start -5.85 -10.05) (end -5.85 5.1) (layer F.CrtYd) (width 0.05))
(fp_line (start -5.85 5.1) (end 11.85 5.1) (layer F.CrtYd) (width 0.05))
(fp_line (start 11.85 5.1) (end 11.85 -10.05) (layer F.CrtYd) (width 0.05))
(fp_line (start 11.85 -10.05) (end -5.85 -10.05) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 0 -2.5 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad "" thru_hole circle (at -3.3 2.5 270) (size 4.6 4.6) (drill 2.3) (layers *.Cu *.Mask))
(pad "" thru_hole circle (at -3.3 -7.5 270) (size 4.6 4.6) (drill 2.3) (layers *.Cu *.Mask))
(pad 1 thru_hole circle (at 0 0 270) (size 1.8 1.8) (drill 1) (layers *.Cu *.Mask)
(net 49 "Net-(R118-Pad1)"))
(pad 2 thru_hole circle (at 0 -2.5 270) (size 1.8 1.8) (drill 1) (layers *.Cu *.Mask)
(net 17 "Net-(C114-Pad1)"))
(pad 3 thru_hole circle (at 0 -5 270) (size 1.8 1.8) (drill 1) (layers *.Cu *.Mask)
(net 47 "Net-(R113-Pad2)"))
(model ${KISYS3DMOD}/Potentiometer_THT.3dshapes/Potentiometer_Alps_RK09K_Single_Horizontal.wrl
Main: Summing design flaw fixed; better headphone vol. range - Multiple R and C value adaptions - Line Input: No relevant difference between INA134 and own circuit -> LM833 chosen - Signal busses/ summing module inputs fixed - TODO: On-Air Button - TODO: Update PCB layout
2020-12-13 21:02:02 +00:00
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(module c3lingo_unit-footprints:Potentiometer_Alps_RK09K_Double_Vertical locked (layer F.Cu) (tedit 60B15712) (tstamp 5F9FDD2F)
(at 90 165 90)
(descr "Potentiometer, vertical, Alps RK09L Double, http://www.alps.com/prod/info/E/HTML/Potentiometer/RotaryPotentiometers/RK09L/RK09L_list.html")
(tags "Potentiometer vertical Alps RK09L Double")
(path /6016D9DA)
(fp_text reference RV103 (at 4.475 -10.5 90) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value "50K log." (at 4.475 5.5 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 12.6 -9.5) (end -3.65 -9.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 12.6 4.5) (end 12.6 -9.5) (layer F.CrtYd) (width 0.05))
(fp_line (start -3.65 4.5) (end 12.6 4.5) (layer F.CrtYd) (width 0.05))
(fp_line (start -3.65 -9.5) (end -3.65 4.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 12.47 -8.67) (end 12.47 3.67) (layer F.SilkS) (width 0.12))
(fp_line (start 0.88 0.87) (end 0.88 3.67) (layer F.SilkS) (width 0.12))
(fp_line (start 0.88 -1.629) (end 0.88 -0.87) (layer F.SilkS) (width 0.12))
(fp_line (start 0.88 -4.129) (end 0.88 -3.37) (layer F.SilkS) (width 0.12))
(fp_line (start 0.88 -8.67) (end 0.88 -5.871) (layer F.SilkS) (width 0.12))
(fp_line (start 9.455 3.67) (end 12.47 3.67) (layer F.SilkS) (width 0.12))
(fp_line (start 0.88 3.67) (end 5.546 3.67) (layer F.SilkS) (width 0.12))
(fp_line (start 9.455 -8.67) (end 12.47 -8.67) (layer F.SilkS) (width 0.12))
(fp_line (start 0.88 -8.67) (end 5.546 -8.67) (layer F.SilkS) (width 0.12))
(fp_line (start 12.35 -8.55) (end 1 -8.55) (layer F.Fab) (width 0.1))
(fp_line (start 12.35 3.55) (end 12.35 -8.55) (layer F.Fab) (width 0.1))
(fp_line (start 1 3.55) (end 12.35 3.55) (layer F.Fab) (width 0.1))
(fp_line (start 1 -8.55) (end 1 3.55) (layer F.Fab) (width 0.1))
(fp_circle (center 7.5 -2.5) (end 10.5 -2.5) (layer F.Fab) (width 0.1))
(fp_text user %R (at 2 -2.5) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 1 thru_hole circle (at 0 -5 180) (size 1.8 1.8) (drill 1) (layers *.Cu *.Mask)
(net 3 GND))
(pad 6 thru_hole circle (at 0 -2.5 90) (size 1.8 1.8) (drill 1) (layers *.Cu *.Mask))
(pad 3 thru_hole circle (at 0 0 90) (size 1.8 1.8) (drill 1) (layers *.Cu *.Mask)
(net 75 /PreampOut))
(pad 5 thru_hole circle (at -2.5 -5 90) (size 1.8 1.8) (drill 1) (layers *.Cu *.Mask))
(pad 2 thru_hole circle (at -2.5 0 90) (size 1.8 1.8) (drill 1) (layers *.Cu *.Mask)
(net 45 "Net-(R108-Pad2)"))
(pad "" np_thru_hole circle (at 7.5 -7.25 90) (size 4 4) (drill 2) (layers *.Cu *.Mask))
(pad "" np_thru_hole circle (at 7.5 2.25 90) (size 4 4) (drill 2) (layers *.Cu *.Mask))
(model ${KISYS3DMOD}/Potentiometer_THT.3dshapes/Potentiometer_Alps_RK09L_Double_Vertical.wrl
Main: Summing design flaw fixed; better headphone vol. range - Multiple R and C value adaptions - Line Input: No relevant difference between INA134 and own circuit -> LM833 chosen - Signal busses/ summing module inputs fixed - TODO: On-Air Button - TODO: Update PCB layout
2020-12-13 21:02:02 +00:00
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(module Potentiometer_THT:Potentiometer_Alps_RK09K_Single_Vertical locked (layer F.Cu) (tedit 5A3D4993) (tstamp 5F9FDF1F)
(at 70.5 92 90)
(descr "Potentiometer, vertical, Alps RK09K Single, http://www.alps.com/prod/info/E/HTML/Potentiometer/RotaryPotentiometers/RK09K/RK09K_list.html")
(tags "Potentiometer vertical Alps RK09K Single")
(path /60B0D55A)
(fp_text reference RV102 (at 6.05 -10.15 90) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value "10K log." (at 6.05 5.15 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_circle (center 7.5 -2.5) (end 10.5 -2.5) (layer F.Fab) (width 0.1))
(fp_line (start 1 -7.4) (end 1 2.4) (layer F.Fab) (width 0.1))
(fp_line (start 1 2.4) (end 13 2.4) (layer F.Fab) (width 0.1))
(fp_line (start 13 2.4) (end 13 -7.4) (layer F.Fab) (width 0.1))
(fp_line (start 13 -7.4) (end 1 -7.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.88 -7.521) (end 4.817 -7.521) (layer F.SilkS) (width 0.12))
(fp_line (start 9.184 -7.521) (end 13.12 -7.521) (layer F.SilkS) (width 0.12))
(fp_line (start 0.88 2.52) (end 4.817 2.52) (layer F.SilkS) (width 0.12))
(fp_line (start 9.184 2.52) (end 13.12 2.52) (layer F.SilkS) (width 0.12))
(fp_line (start 0.88 -7.521) (end 0.88 -5.871) (layer F.SilkS) (width 0.12))
(fp_line (start 0.88 -4.129) (end 0.88 -3.37) (layer F.SilkS) (width 0.12))
(fp_line (start 0.88 -1.629) (end 0.88 -0.87) (layer F.SilkS) (width 0.12))
(fp_line (start 0.88 0.87) (end 0.88 2.52) (layer F.SilkS) (width 0.12))
(fp_line (start 13.12 -7.521) (end 13.12 2.52) (layer F.SilkS) (width 0.12))
(fp_line (start -1.15 -9.15) (end -1.15 4.15) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.15 4.15) (end 13.25 4.15) (layer F.CrtYd) (width 0.05))
(fp_line (start 13.25 4.15) (end 13.25 -9.15) (layer F.CrtYd) (width 0.05))
(fp_line (start 13.25 -9.15) (end -1.15 -9.15) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 2 -2.5) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad "" np_thru_hole circle (at 7 1.9 90) (size 4 4) (drill 2) (layers *.Cu *.Mask))
(pad "" np_thru_hole circle (at 7 -6.9 90) (size 4 4) (drill 2) (layers *.Cu *.Mask))
(pad 1 thru_hole circle (at 0 0 90) (size 1.8 1.8) (drill 1) (layers *.Cu *.Mask)
(net 44 "Net-(R105-Pad1)"))
(pad 2 thru_hole circle (at 0 -2.5 90) (size 1.8 1.8) (drill 1) (layers *.Cu *.Mask)
(net 75 /PreampOut))
(pad 3 thru_hole circle (at 0 -5 90) (size 1.8 1.8) (drill 1) (layers *.Cu *.Mask))
(model ${KISYS3DMOD}/Potentiometer_THT.3dshapes/Potentiometer_Alps_RK09K_Single_Vertical.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
Main: Summing design flaw fixed; better headphone vol. range - Multiple R and C value adaptions - Line Input: No relevant difference between INA134 and own circuit -> LM833 chosen - Signal busses/ summing module inputs fixed - TODO: On-Air Button - TODO: Update PCB layout
2020-12-13 21:02:02 +00:00
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
)
(module c3lingo_unit-footprints:Potentiometer_Alps_RK09K_Double_Vertical locked (layer F.Cu) (tedit 60B15712) (tstamp 5F9FDD0B)
(at 70.5 165 90)
(descr "Potentiometer, vertical, Alps RK09L Double, http://www.alps.com/prod/info/E/HTML/Potentiometer/RotaryPotentiometers/RK09L/RK09L_list.html")
(tags "Potentiometer vertical Alps RK09L Double")
(path /5FFF6755)
(fp_text reference RV101 (at 4.475 -10.5 90) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value "50K log." (at 4.475 5.5 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 12.6 -9.5) (end -3.65 -9.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 12.6 4.5) (end 12.6 -9.5) (layer F.CrtYd) (width 0.05))
(fp_line (start -3.65 4.5) (end 12.6 4.5) (layer F.CrtYd) (width 0.05))
(fp_line (start -3.65 -9.5) (end -3.65 4.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 12.47 -8.67) (end 12.47 3.67) (layer F.SilkS) (width 0.12))
(fp_line (start 0.88 0.87) (end 0.88 3.67) (layer F.SilkS) (width 0.12))
(fp_line (start 0.88 -1.629) (end 0.88 -0.87) (layer F.SilkS) (width 0.12))
(fp_line (start 0.88 -4.129) (end 0.88 -3.37) (layer F.SilkS) (width 0.12))
(fp_line (start 0.88 -8.67) (end 0.88 -5.871) (layer F.SilkS) (width 0.12))
(fp_line (start 9.455 3.67) (end 12.47 3.67) (layer F.SilkS) (width 0.12))
(fp_line (start 0.88 3.67) (end 5.546 3.67) (layer F.SilkS) (width 0.12))
(fp_line (start 9.455 -8.67) (end 12.47 -8.67) (layer F.SilkS) (width 0.12))
(fp_line (start 0.88 -8.67) (end 5.546 -8.67) (layer F.SilkS) (width 0.12))
(fp_line (start 12.35 -8.55) (end 1 -8.55) (layer F.Fab) (width 0.1))
(fp_line (start 12.35 3.55) (end 12.35 -8.55) (layer F.Fab) (width 0.1))
(fp_line (start 1 3.55) (end 12.35 3.55) (layer F.Fab) (width 0.1))
(fp_line (start 1 -8.55) (end 1 3.55) (layer F.Fab) (width 0.1))
(fp_circle (center 7.5 -2.5) (end 10.5 -2.5) (layer F.Fab) (width 0.1))
(fp_text user %R (at 2 -2.5) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 1 thru_hole circle (at 0 -5 180) (size 1.8 1.8) (drill 1) (layers *.Cu *.Mask)
(net 3 GND))
(pad 6 thru_hole circle (at 0 -2.5 90) (size 1.8 1.8) (drill 1) (layers *.Cu *.Mask))
(pad 3 thru_hole circle (at 0 0 90) (size 1.8 1.8) (drill 1) (layers *.Cu *.Mask)
(net 41 /Monitor_Stage))
(pad 5 thru_hole circle (at -2.5 -5 90) (size 1.8 1.8) (drill 1) (layers *.Cu *.Mask))
(pad 2 thru_hole circle (at -2.5 0 90) (size 1.8 1.8) (drill 1) (layers *.Cu *.Mask)
(net 42 "Net-(R101-Pad2)"))
(pad "" np_thru_hole circle (at 7.5 -7.25 90) (size 4 4) (drill 2) (layers *.Cu *.Mask))
(pad "" np_thru_hole circle (at 7.5 2.25 90) (size 4 4) (drill 2) (layers *.Cu *.Mask))
(model ${KISYS3DMOD}/Potentiometer_THT.3dshapes/Potentiometer_Alps_RK09L_Double_Vertical.wrl
Main: Summing design flaw fixed; better headphone vol. range - Multiple R and C value adaptions - Line Input: No relevant difference between INA134 and own circuit -> LM833 chosen - Signal busses/ summing module inputs fixed - TODO: On-Air Button - TODO: Update PCB layout
2020-12-13 21:02:02 +00:00
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(module Resistor_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal (layer F.Cu) (tedit 5AE5139B) (tstamp 60B1C9C0)
(at 113.03 129.54)
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
(descr "Resistor, Axial_DIN0207 series, Axial, Horizontal, pin pitch=10.16mm, 0.25W = 1/4W, length*diameter=6.3*2.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf")
(tags "Resistor Axial_DIN0207 series Axial Horizontal pin pitch 10.16mm 0.25W = 1/4W length 6.3mm diameter 2.5mm")
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(path /60B4292A)
(fp_text reference R147 (at 5.08 -2.37) (layer F.SilkS)
Main: Summing design flaw fixed; better headphone vol. range - Multiple R and C value adaptions - Line Input: No relevant difference between INA134 and own circuit -> LM833 chosen - Signal busses/ summing module inputs fixed - TODO: On-Air Button - TODO: Update PCB layout
2020-12-13 21:02:02 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(fp_text value 100K (at 5.08 2.37) (layer F.Fab)
Main: Summing design flaw fixed; better headphone vol. range - Multiple R and C value adaptions - Line Input: No relevant difference between INA134 and own circuit -> LM833 chosen - Signal busses/ summing module inputs fixed - TODO: On-Air Button - TODO: Update PCB layout
2020-12-13 21:02:02 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
(fp_line (start 1.93 -1.25) (end 1.93 1.25) (layer F.Fab) (width 0.1))
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(fp_line (start 1.93 1.25) (end 8.23 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 1.25) (end 8.23 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 -1.25) (end 1.93 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 0 0) (end 1.93 0) (layer F.Fab) (width 0.1))
(fp_line (start 10.16 0) (end 8.23 0) (layer F.Fab) (width 0.1))
(fp_line (start 1.81 -1.37) (end 1.81 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 1.81 1.37) (end 8.35 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 8.35 1.37) (end 8.35 -1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 8.35 -1.37) (end 1.81 -1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 1.04 0) (end 1.81 0) (layer F.SilkS) (width 0.12))
(fp_line (start 9.12 0) (end 8.35 0) (layer F.SilkS) (width 0.12))
(fp_line (start -1.05 -1.5) (end -1.05 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.5) (end 11.21 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 11.21 1.5) (end 11.21 -1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 11.21 -1.5) (end -1.05 -1.5) (layer F.CrtYd) (width 0.05))
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
(fp_text user %R (at 5.08 0) (layer F.Fab)
Main: Summing design flaw fixed; better headphone vol. range - Multiple R and C value adaptions - Line Input: No relevant difference between INA134 and own circuit -> LM833 chosen - Signal busses/ summing module inputs fixed - TODO: On-Air Button - TODO: Update PCB layout
2020-12-13 21:02:02 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
(pad 2 thru_hole oval (at 10.16 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(net 3 GND))
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
(pad 1 thru_hole circle (at 0 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(net 20 "Net-(C120-Pad1)"))
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
(model ${KISYS3DMOD}/Resistor_THT.3dshapes/R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal.wrl
Refine headphone mix requirements, fix signal flow
2020-11-12 00:11:14 +00:00
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
Schematic Main: Add corrected headphone amp
2020-11-09 22:22:35 +00:00
)
Refine headphone mix requirements, fix signal flow
2020-11-12 00:11:14 +00:00
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(module Resistor_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal (layer F.Cu) (tedit 5AE5139B) (tstamp 60B1C9A9)
(at 113.03 55.88)
(descr "Resistor, Axial_DIN0207 series, Axial, Horizontal, pin pitch=10.16mm, 0.25W = 1/4W, length*diameter=6.3*2.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf")
(tags "Resistor Axial_DIN0207 series Axial Horizontal pin pitch 10.16mm 0.25W = 1/4W length 6.3mm diameter 2.5mm")
(path /60B429EA)
(fp_text reference R146 (at 5.08 -2.37) (layer F.SilkS)
Schematic Main: Add corrected headphone amp
2020-11-09 22:22:35 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(fp_text value 2.7K (at 5.08 2.37) (layer F.Fab)
Schematic Main: Add corrected headphone amp
2020-11-09 22:22:35 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(fp_line (start 1.93 -1.25) (end 1.93 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 1.93 1.25) (end 8.23 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 1.25) (end 8.23 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 -1.25) (end 1.93 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 0 0) (end 1.93 0) (layer F.Fab) (width 0.1))
(fp_line (start 10.16 0) (end 8.23 0) (layer F.Fab) (width 0.1))
(fp_line (start 1.81 -1.37) (end 1.81 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 1.81 1.37) (end 8.35 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 8.35 1.37) (end 8.35 -1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 8.35 -1.37) (end 1.81 -1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 1.04 0) (end 1.81 0) (layer F.SilkS) (width 0.12))
(fp_line (start 9.12 0) (end 8.35 0) (layer F.SilkS) (width 0.12))
(fp_line (start -1.05 -1.5) (end -1.05 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.5) (end 11.21 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 11.21 1.5) (end 11.21 -1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 11.21 -1.5) (end -1.05 -1.5) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 5.08 0) (layer F.Fab)
Schematic: Bugfixes, VU meter draft, first development PCB draft
2020-11-02 00:00:47 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(pad 2 thru_hole oval (at 10.16 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 2 +15V))
(pad 1 thru_hole circle (at 0 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 74 "Net-(R145-Pad2)"))
(model ${KISYS3DMOD}/Resistor_THT.3dshapes/R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal.wrl
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
Schematic: Bugfixes, VU meter draft, first development PCB draft
2020-11-02 00:00:47 +00:00
)
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(module Resistor_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal (layer F.Cu) (tedit 5AE5139B) (tstamp 60B1C992)
(at 113.03 60.96)
(descr "Resistor, Axial_DIN0207 series, Axial, Horizontal, pin pitch=10.16mm, 0.25W = 1/4W, length*diameter=6.3*2.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf")
(tags "Resistor Axial_DIN0207 series Axial Horizontal pin pitch 10.16mm 0.25W = 1/4W length 6.3mm diameter 2.5mm")
(path /60B4275E)
(fp_text reference R145 (at 5.08 -2.37) (layer F.SilkS)
Schematic: Bugfixes, VU meter draft, first development PCB draft
2020-11-02 00:00:47 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(fp_text value 3.9K (at 5.08 2.37) (layer F.Fab)
Schematic: Bugfixes, VU meter draft, first development PCB draft
2020-11-02 00:00:47 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(fp_line (start 1.93 -1.25) (end 1.93 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 1.93 1.25) (end 8.23 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 1.25) (end 8.23 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 -1.25) (end 1.93 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 0 0) (end 1.93 0) (layer F.Fab) (width 0.1))
(fp_line (start 10.16 0) (end 8.23 0) (layer F.Fab) (width 0.1))
(fp_line (start 1.81 -1.37) (end 1.81 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 1.81 1.37) (end 8.35 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 8.35 1.37) (end 8.35 -1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 8.35 -1.37) (end 1.81 -1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 1.04 0) (end 1.81 0) (layer F.SilkS) (width 0.12))
(fp_line (start 9.12 0) (end 8.35 0) (layer F.SilkS) (width 0.12))
(fp_line (start -1.05 -1.5) (end -1.05 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.5) (end 11.21 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 11.21 1.5) (end 11.21 -1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 11.21 -1.5) (end -1.05 -1.5) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 5.08 0) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 2 thru_hole oval (at 10.16 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 74 "Net-(R145-Pad2)"))
(pad 1 thru_hole circle (at 0 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 73 "Net-(R144-Pad2)"))
(model ${KISYS3DMOD}/Resistor_THT.3dshapes/R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Resistor_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal (layer F.Cu) (tedit 5AE5139B) (tstamp 60B1C97B)
(at 113.03 66.04)
(descr "Resistor, Axial_DIN0207 series, Axial, Horizontal, pin pitch=10.16mm, 0.25W = 1/4W, length*diameter=6.3*2.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf")
(tags "Resistor Axial_DIN0207 series Axial Horizontal pin pitch 10.16mm 0.25W = 1/4W length 6.3mm diameter 2.5mm")
(path /60B42774)
(fp_text reference R144 (at 5.08 -2.37) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 2.7K (at 5.08 2.37) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 1.93 -1.25) (end 1.93 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 1.93 1.25) (end 8.23 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 1.25) (end 8.23 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 -1.25) (end 1.93 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 0 0) (end 1.93 0) (layer F.Fab) (width 0.1))
(fp_line (start 10.16 0) (end 8.23 0) (layer F.Fab) (width 0.1))
(fp_line (start 1.81 -1.37) (end 1.81 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 1.81 1.37) (end 8.35 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 8.35 1.37) (end 8.35 -1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 8.35 -1.37) (end 1.81 -1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 1.04 0) (end 1.81 0) (layer F.SilkS) (width 0.12))
(fp_line (start 9.12 0) (end 8.35 0) (layer F.SilkS) (width 0.12))
(fp_line (start -1.05 -1.5) (end -1.05 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.5) (end 11.21 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 11.21 1.5) (end 11.21 -1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 11.21 -1.5) (end -1.05 -1.5) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 5.08 0) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 2 thru_hole oval (at 10.16 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 73 "Net-(R144-Pad2)"))
(pad 1 thru_hole circle (at 0 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 72 "Net-(R143-Pad2)"))
(model ${KISYS3DMOD}/Resistor_THT.3dshapes/R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Resistor_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal (layer F.Cu) (tedit 5AE5139B) (tstamp 60B1C964)
(at 113.03 71.12)
(descr "Resistor, Axial_DIN0207 series, Axial, Horizontal, pin pitch=10.16mm, 0.25W = 1/4W, length*diameter=6.3*2.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf")
(tags "Resistor Axial_DIN0207 series Axial Horizontal pin pitch 10.16mm 0.25W = 1/4W length 6.3mm diameter 2.5mm")
(path /60B4277F)
(fp_text reference R143 (at 5.08 -2.37) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 1.5K (at 5.08 2.37) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 1.93 -1.25) (end 1.93 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 1.93 1.25) (end 8.23 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 1.25) (end 8.23 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 -1.25) (end 1.93 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 0 0) (end 1.93 0) (layer F.Fab) (width 0.1))
(fp_line (start 10.16 0) (end 8.23 0) (layer F.Fab) (width 0.1))
(fp_line (start 1.81 -1.37) (end 1.81 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 1.81 1.37) (end 8.35 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 8.35 1.37) (end 8.35 -1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 8.35 -1.37) (end 1.81 -1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 1.04 0) (end 1.81 0) (layer F.SilkS) (width 0.12))
(fp_line (start 9.12 0) (end 8.35 0) (layer F.SilkS) (width 0.12))
(fp_line (start -1.05 -1.5) (end -1.05 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.5) (end 11.21 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 11.21 1.5) (end 11.21 -1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 11.21 -1.5) (end -1.05 -1.5) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 5.08 0) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 2 thru_hole oval (at 10.16 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 72 "Net-(R143-Pad2)"))
(pad 1 thru_hole circle (at 0 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 71 "Net-(R142-Pad2)"))
(model ${KISYS3DMOD}/Resistor_THT.3dshapes/R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Resistor_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal (layer F.Cu) (tedit 5AE5139B) (tstamp 60B1C94D)
(at 113.03 76.2)
(descr "Resistor, Axial_DIN0207 series, Axial, Horizontal, pin pitch=10.16mm, 0.25W = 1/4W, length*diameter=6.3*2.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf")
(tags "Resistor Axial_DIN0207 series Axial Horizontal pin pitch 10.16mm 0.25W = 1/4W length 6.3mm diameter 2.5mm")
(path /60B4276B)
(fp_text reference R142 (at 5.08 -2.37) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 1K (at 5.08 2.37) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 1.93 -1.25) (end 1.93 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 1.93 1.25) (end 8.23 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 1.25) (end 8.23 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 -1.25) (end 1.93 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 0 0) (end 1.93 0) (layer F.Fab) (width 0.1))
(fp_line (start 10.16 0) (end 8.23 0) (layer F.Fab) (width 0.1))
(fp_line (start 1.81 -1.37) (end 1.81 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 1.81 1.37) (end 8.35 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 8.35 1.37) (end 8.35 -1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 8.35 -1.37) (end 1.81 -1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 1.04 0) (end 1.81 0) (layer F.SilkS) (width 0.12))
(fp_line (start 9.12 0) (end 8.35 0) (layer F.SilkS) (width 0.12))
(fp_line (start -1.05 -1.5) (end -1.05 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.5) (end 11.21 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 11.21 1.5) (end 11.21 -1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 11.21 -1.5) (end -1.05 -1.5) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 5.08 0) (layer F.Fab)
Schematic: Bugfixes, VU meter draft, first development PCB draft
2020-11-02 00:00:47 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(pad 2 thru_hole oval (at 10.16 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 71 "Net-(R142-Pad2)"))
(pad 1 thru_hole circle (at 0 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 70 "Net-(R141-Pad2)"))
(model ${KISYS3DMOD}/Resistor_THT.3dshapes/R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal.wrl
Refine headphone mix requirements, fix signal flow
2020-11-12 00:11:14 +00:00
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
Schematic: Bugfixes, VU meter draft, first development PCB draft
2020-11-02 00:00:47 +00:00
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(module Resistor_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal (layer F.Cu) (tedit 5AE5139B) (tstamp 60B1C936)
(at 113.03 81.28)
(descr "Resistor, Axial_DIN0207 series, Axial, Horizontal, pin pitch=10.16mm, 0.25W = 1/4W, length*diameter=6.3*2.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf")
(tags "Resistor Axial_DIN0207 series Axial Horizontal pin pitch 10.16mm 0.25W = 1/4W length 6.3mm diameter 2.5mm")
(path /60B427A4)
(fp_text reference R141 (at 5.08 -2.37) (layer F.SilkS)
Schematic: Bugfixes, VU meter draft, first development PCB draft
2020-11-02 00:00:47 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(fp_text value 680R (at 5.08 2.37) (layer F.Fab)
final fixes for first prototype PCB order
2020-11-12 23:40:18 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(fp_line (start 1.93 -1.25) (end 1.93 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 1.93 1.25) (end 8.23 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 1.25) (end 8.23 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 -1.25) (end 1.93 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 0 0) (end 1.93 0) (layer F.Fab) (width 0.1))
(fp_line (start 10.16 0) (end 8.23 0) (layer F.Fab) (width 0.1))
(fp_line (start 1.81 -1.37) (end 1.81 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 1.81 1.37) (end 8.35 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 8.35 1.37) (end 8.35 -1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 8.35 -1.37) (end 1.81 -1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 1.04 0) (end 1.81 0) (layer F.SilkS) (width 0.12))
(fp_line (start 9.12 0) (end 8.35 0) (layer F.SilkS) (width 0.12))
(fp_line (start -1.05 -1.5) (end -1.05 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.5) (end 11.21 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 11.21 1.5) (end 11.21 -1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 11.21 -1.5) (end -1.05 -1.5) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 5.08 0) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 2 thru_hole oval (at 10.16 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 70 "Net-(R141-Pad2)"))
(pad 1 thru_hole circle (at 0 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 69 "Net-(R140-Pad2)"))
(model ${KISYS3DMOD}/Resistor_THT.3dshapes/R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Resistor_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal (layer F.Cu) (tedit 5AE5139B) (tstamp 60B1C91F)
(at 113.03 86.36)
(descr "Resistor, Axial_DIN0207 series, Axial, Horizontal, pin pitch=10.16mm, 0.25W = 1/4W, length*diameter=6.3*2.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf")
(tags "Resistor Axial_DIN0207 series Axial Horizontal pin pitch 10.16mm 0.25W = 1/4W length 6.3mm diameter 2.5mm")
(path /60B427BA)
(fp_text reference R140 (at 5.08 -2.37) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 390R (at 5.08 2.37) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 1.93 -1.25) (end 1.93 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 1.93 1.25) (end 8.23 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 1.25) (end 8.23 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 -1.25) (end 1.93 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 0 0) (end 1.93 0) (layer F.Fab) (width 0.1))
(fp_line (start 10.16 0) (end 8.23 0) (layer F.Fab) (width 0.1))
(fp_line (start 1.81 -1.37) (end 1.81 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 1.81 1.37) (end 8.35 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 8.35 1.37) (end 8.35 -1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 8.35 -1.37) (end 1.81 -1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 1.04 0) (end 1.81 0) (layer F.SilkS) (width 0.12))
(fp_line (start 9.12 0) (end 8.35 0) (layer F.SilkS) (width 0.12))
(fp_line (start -1.05 -1.5) (end -1.05 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.5) (end 11.21 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 11.21 1.5) (end 11.21 -1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 11.21 -1.5) (end -1.05 -1.5) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 5.08 0) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 2 thru_hole oval (at 10.16 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 69 "Net-(R140-Pad2)"))
(pad 1 thru_hole circle (at 0 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 68 "Net-(R139-Pad2)"))
(model ${KISYS3DMOD}/Resistor_THT.3dshapes/R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Resistor_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal (layer F.Cu) (tedit 5AE5139B) (tstamp 60B1C908)
(at 113.03 91.44)
(descr "Resistor, Axial_DIN0207 series, Axial, Horizontal, pin pitch=10.16mm, 0.25W = 1/4W, length*diameter=6.3*2.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf")
(tags "Resistor Axial_DIN0207 series Axial Horizontal pin pitch 10.16mm 0.25W = 1/4W length 6.3mm diameter 2.5mm")
(path /60B427C5)
(fp_text reference R139 (at 5.08 -2.37) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 270R (at 5.08 2.37) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 1.93 -1.25) (end 1.93 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 1.93 1.25) (end 8.23 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 1.25) (end 8.23 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 -1.25) (end 1.93 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 0 0) (end 1.93 0) (layer F.Fab) (width 0.1))
(fp_line (start 10.16 0) (end 8.23 0) (layer F.Fab) (width 0.1))
(fp_line (start 1.81 -1.37) (end 1.81 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 1.81 1.37) (end 8.35 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 8.35 1.37) (end 8.35 -1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 8.35 -1.37) (end 1.81 -1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 1.04 0) (end 1.81 0) (layer F.SilkS) (width 0.12))
(fp_line (start 9.12 0) (end 8.35 0) (layer F.SilkS) (width 0.12))
(fp_line (start -1.05 -1.5) (end -1.05 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.5) (end 11.21 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 11.21 1.5) (end 11.21 -1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 11.21 -1.5) (end -1.05 -1.5) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 5.08 0) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 2 thru_hole oval (at 10.16 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 68 "Net-(R139-Pad2)"))
(pad 1 thru_hole circle (at 0 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 67 "Net-(R138-Pad2)"))
(model ${KISYS3DMOD}/Resistor_THT.3dshapes/R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Resistor_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal (layer F.Cu) (tedit 5AE5139B) (tstamp 60B1C8F1)
(at 113.03 96.52)
(descr "Resistor, Axial_DIN0207 series, Axial, Horizontal, pin pitch=10.16mm, 0.25W = 1/4W, length*diameter=6.3*2.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf")
(tags "Resistor Axial_DIN0207 series Axial Horizontal pin pitch 10.16mm 0.25W = 1/4W length 6.3mm diameter 2.5mm")
(path /60B427B1)
(fp_text reference R138 (at 5.08 -2.37) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 150R (at 5.08 2.37) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 1.93 -1.25) (end 1.93 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 1.93 1.25) (end 8.23 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 1.25) (end 8.23 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 -1.25) (end 1.93 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 0 0) (end 1.93 0) (layer F.Fab) (width 0.1))
(fp_line (start 10.16 0) (end 8.23 0) (layer F.Fab) (width 0.1))
(fp_line (start 1.81 -1.37) (end 1.81 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 1.81 1.37) (end 8.35 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 8.35 1.37) (end 8.35 -1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 8.35 -1.37) (end 1.81 -1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 1.04 0) (end 1.81 0) (layer F.SilkS) (width 0.12))
(fp_line (start 9.12 0) (end 8.35 0) (layer F.SilkS) (width 0.12))
(fp_line (start -1.05 -1.5) (end -1.05 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.5) (end 11.21 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 11.21 1.5) (end 11.21 -1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 11.21 -1.5) (end -1.05 -1.5) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 5.08 0) (layer F.Fab)
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(pad 2 thru_hole oval (at 10.16 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 67 "Net-(R138-Pad2)"))
(pad 1 thru_hole circle (at 0 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 66 "Net-(R137-Pad2)"))
(model ${KISYS3DMOD}/Resistor_THT.3dshapes/R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal.wrl
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
Refine headphone mix requirements, fix signal flow
2020-11-12 00:11:14 +00:00
)
Schematic: Bugfixes, VU meter draft, first development PCB draft
2020-11-02 00:00:47 +00:00
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(module Resistor_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal (layer F.Cu) (tedit 5AE5139B) (tstamp 60B1C8DA)
(at 113.03 101.6)
Refine headphone mix requirements, fix signal flow
2020-11-12 00:11:14 +00:00
(descr "Resistor, Axial_DIN0207 series, Axial, Horizontal, pin pitch=10.16mm, 0.25W = 1/4W, length*diameter=6.3*2.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf")
(tags "Resistor Axial_DIN0207 series Axial Horizontal pin pitch 10.16mm 0.25W = 1/4W length 6.3mm diameter 2.5mm")
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(path /60B427EA)
(fp_text reference R137 (at 5.08 -2.37) (layer F.SilkS)
Schematic: Bugfixes, VU meter draft, first development PCB draft
2020-11-02 00:00:47 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(fp_text value 100R (at 5.08 2.37) (layer F.Fab)
Schematic: Bugfixes, VU meter draft, first development PCB draft
2020-11-02 00:00:47 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
(fp_line (start 1.93 -1.25) (end 1.93 1.25) (layer F.Fab) (width 0.1))
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(fp_line (start 1.93 1.25) (end 8.23 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 1.25) (end 8.23 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 -1.25) (end 1.93 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 0 0) (end 1.93 0) (layer F.Fab) (width 0.1))
(fp_line (start 10.16 0) (end 8.23 0) (layer F.Fab) (width 0.1))
(fp_line (start 1.81 -1.37) (end 1.81 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 1.81 1.37) (end 8.35 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 8.35 1.37) (end 8.35 -1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 8.35 -1.37) (end 1.81 -1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 1.04 0) (end 1.81 0) (layer F.SilkS) (width 0.12))
(fp_line (start 9.12 0) (end 8.35 0) (layer F.SilkS) (width 0.12))
(fp_line (start -1.05 -1.5) (end -1.05 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.5) (end 11.21 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 11.21 1.5) (end 11.21 -1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 11.21 -1.5) (end -1.05 -1.5) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 5.08 0) (layer F.Fab)
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(pad 2 thru_hole oval (at 10.16 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 66 "Net-(R137-Pad2)"))
(pad 1 thru_hole circle (at 0 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 65 "Net-(R136-Pad2)"))
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
(model ${KISYS3DMOD}/Resistor_THT.3dshapes/R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(module Resistor_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal (layer F.Cu) (tedit 5AE5139B) (tstamp 60B1C8C3)
(at 113.03 106.68)
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
(descr "Resistor, Axial_DIN0207 series, Axial, Horizontal, pin pitch=10.16mm, 0.25W = 1/4W, length*diameter=6.3*2.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf")
(tags "Resistor Axial_DIN0207 series Axial Horizontal pin pitch 10.16mm 0.25W = 1/4W length 6.3mm diameter 2.5mm")
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(path /60B427FE)
(fp_text reference R136 (at 5.08 -2.37) (layer F.SilkS)
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(fp_text value 68R (at 5.08 2.37) (layer F.Fab)
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 1.93 -1.25) (end 1.93 1.25) (layer F.Fab) (width 0.1))
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(fp_line (start 1.93 1.25) (end 8.23 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 1.25) (end 8.23 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 -1.25) (end 1.93 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 0 0) (end 1.93 0) (layer F.Fab) (width 0.1))
(fp_line (start 10.16 0) (end 8.23 0) (layer F.Fab) (width 0.1))
(fp_line (start 1.81 -1.37) (end 1.81 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 1.81 1.37) (end 8.35 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 8.35 1.37) (end 8.35 -1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 8.35 -1.37) (end 1.81 -1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 1.04 0) (end 1.81 0) (layer F.SilkS) (width 0.12))
(fp_line (start 9.12 0) (end 8.35 0) (layer F.SilkS) (width 0.12))
(fp_line (start -1.05 -1.5) (end -1.05 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.5) (end 11.21 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 11.21 1.5) (end 11.21 -1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 11.21 -1.5) (end -1.05 -1.5) (layer F.CrtYd) (width 0.05))
Refine headphone mix requirements, fix signal flow
2020-11-12 00:11:14 +00:00
(fp_text user %R (at 5.08 0) (layer F.Fab)
Schematic: Bugfixes, VU meter draft, first development PCB draft
2020-11-02 00:00:47 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Refine headphone mix requirements, fix signal flow
2020-11-12 00:11:14 +00:00
(pad 2 thru_hole oval (at 10.16 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(net 65 "Net-(R136-Pad2)"))
Refine headphone mix requirements, fix signal flow
2020-11-12 00:11:14 +00:00
(pad 1 thru_hole circle (at 0 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(net 64 "Net-(R135-Pad2)"))
Refine headphone mix requirements, fix signal flow
2020-11-12 00:11:14 +00:00
(model ${KISYS3DMOD}/Resistor_THT.3dshapes/R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
Schematic: Bugfixes, VU meter draft, first development PCB draft
2020-11-02 00:00:47 +00:00
)
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(module Resistor_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal (layer F.Cu) (tedit 5AE5139B) (tstamp 60B1C8AC)
(at 113.03 111.76)
Refine headphone mix requirements, fix signal flow
2020-11-12 00:11:14 +00:00
(descr "Resistor, Axial_DIN0207 series, Axial, Horizontal, pin pitch=10.16mm, 0.25W = 1/4W, length*diameter=6.3*2.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf")
(tags "Resistor Axial_DIN0207 series Axial Horizontal pin pitch 10.16mm 0.25W = 1/4W length 6.3mm diameter 2.5mm")
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(path /60B42809)
(fp_text reference R135 (at 5.08 -2.37) (layer F.SilkS)
Schematic: Bugfixes, VU meter draft, first development PCB draft
2020-11-02 00:00:47 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(fp_text value 39R (at 5.08 2.37) (layer F.Fab)
Schematic: Bugfixes, VU meter draft, first development PCB draft
2020-11-02 00:00:47 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(fp_line (start 1.93 -1.25) (end 1.93 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 1.93 1.25) (end 8.23 1.25) (layer F.Fab) (width 0.1))
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
(fp_line (start 8.23 1.25) (end 8.23 -1.25) (layer F.Fab) (width 0.1))
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(fp_line (start 8.23 -1.25) (end 1.93 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 0 0) (end 1.93 0) (layer F.Fab) (width 0.1))
(fp_line (start 10.16 0) (end 8.23 0) (layer F.Fab) (width 0.1))
(fp_line (start 1.81 -1.37) (end 1.81 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 1.81 1.37) (end 8.35 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 8.35 1.37) (end 8.35 -1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 8.35 -1.37) (end 1.81 -1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 1.04 0) (end 1.81 0) (layer F.SilkS) (width 0.12))
(fp_line (start 9.12 0) (end 8.35 0) (layer F.SilkS) (width 0.12))
(fp_line (start -1.05 -1.5) (end -1.05 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.5) (end 11.21 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 11.21 1.5) (end 11.21 -1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 11.21 -1.5) (end -1.05 -1.5) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 5.08 0) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 2 thru_hole oval (at 10.16 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 64 "Net-(R135-Pad2)"))
(pad 1 thru_hole circle (at 0 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 63 "Net-(R134-Pad2)"))
(model ${KISYS3DMOD}/Resistor_THT.3dshapes/R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Resistor_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal (layer F.Cu) (tedit 5AE5139B) (tstamp 60B1C895)
(at 113.03 116.84)
(descr "Resistor, Axial_DIN0207 series, Axial, Horizontal, pin pitch=10.16mm, 0.25W = 1/4W, length*diameter=6.3*2.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf")
(tags "Resistor Axial_DIN0207 series Axial Horizontal pin pitch 10.16mm 0.25W = 1/4W length 6.3mm diameter 2.5mm")
(path /60B427F7)
(fp_text reference R134 (at 5.08 -2.37) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 68R (at 5.08 2.37) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 1.93 -1.25) (end 1.93 1.25) (layer F.Fab) (width 0.1))
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
(fp_line (start 1.93 1.25) (end 8.23 1.25) (layer F.Fab) (width 0.1))
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(fp_line (start 8.23 1.25) (end 8.23 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 -1.25) (end 1.93 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 0 0) (end 1.93 0) (layer F.Fab) (width 0.1))
(fp_line (start 10.16 0) (end 8.23 0) (layer F.Fab) (width 0.1))
(fp_line (start 1.81 -1.37) (end 1.81 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 1.81 1.37) (end 8.35 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 8.35 1.37) (end 8.35 -1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 8.35 -1.37) (end 1.81 -1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 1.04 0) (end 1.81 0) (layer F.SilkS) (width 0.12))
(fp_line (start 9.12 0) (end 8.35 0) (layer F.SilkS) (width 0.12))
(fp_line (start -1.05 -1.5) (end -1.05 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.5) (end 11.21 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 11.21 1.5) (end 11.21 -1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 11.21 -1.5) (end -1.05 -1.5) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 5.08 0) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 2 thru_hole oval (at 10.16 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 63 "Net-(R134-Pad2)"))
(pad 1 thru_hole circle (at 0 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 3 GND))
(model ${KISYS3DMOD}/Resistor_THT.3dshapes/R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Resistor_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal (layer F.Cu) (tedit 5AE5139B) (tstamp 60B1C87E)
(at 97.79 143.51)
(descr "Resistor, Axial_DIN0207 series, Axial, Horizontal, pin pitch=10.16mm, 0.25W = 1/4W, length*diameter=6.3*2.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf")
(tags "Resistor Axial_DIN0207 series Axial Horizontal pin pitch 10.16mm 0.25W = 1/4W length 6.3mm diameter 2.5mm")
(path /60B4297D)
(fp_text reference R133 (at 5.08 -2.37) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 1K (at 5.08 2.37) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
(fp_line (start 1.93 -1.25) (end 1.93 1.25) (layer F.Fab) (width 0.1))
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(fp_line (start 1.93 1.25) (end 8.23 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 1.25) (end 8.23 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 -1.25) (end 1.93 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 0 0) (end 1.93 0) (layer F.Fab) (width 0.1))
(fp_line (start 10.16 0) (end 8.23 0) (layer F.Fab) (width 0.1))
(fp_line (start 1.81 -1.37) (end 1.81 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 1.81 1.37) (end 8.35 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 8.35 1.37) (end 8.35 -1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 8.35 -1.37) (end 1.81 -1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 1.04 0) (end 1.81 0) (layer F.SilkS) (width 0.12))
(fp_line (start 9.12 0) (end 8.35 0) (layer F.SilkS) (width 0.12))
(fp_line (start -1.05 -1.5) (end -1.05 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.5) (end 11.21 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 11.21 1.5) (end 11.21 -1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 11.21 -1.5) (end -1.05 -1.5) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 5.08 0) (layer F.Fab)
Main: Summing design flaw fixed; better headphone vol. range - Multiple R and C value adaptions - Line Input: No relevant difference between INA134 and own circuit -> LM833 chosen - Signal busses/ summing module inputs fixed - TODO: On-Air Button - TODO: Update PCB layout
2020-12-13 21:02:02 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(pad 2 thru_hole oval (at 10.16 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 36 "Net-(D118-Pad2)"))
(pad 1 thru_hole circle (at 0 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 18 "Net-(C119-Pad2)"))
Main: Summing design flaw fixed; better headphone vol. range - Multiple R and C value adaptions - Line Input: No relevant difference between INA134 and own circuit -> LM833 chosen - Signal busses/ summing module inputs fixed - TODO: On-Air Button - TODO: Update PCB layout
2020-12-13 21:02:02 +00:00
(model ${KISYS3DMOD}/Resistor_THT.3dshapes/R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(module Resistor_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal (layer F.Cu) (tedit 5AE5139B) (tstamp 60B1C867)
(at 87.63 55.88)
(descr "Resistor, Axial_DIN0207 series, Axial, Horizontal, pin pitch=10.16mm, 0.25W = 1/4W, length*diameter=6.3*2.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf")
(tags "Resistor Axial_DIN0207 series Axial Horizontal pin pitch 10.16mm 0.25W = 1/4W length 6.3mm diameter 2.5mm")
(path /60B42825)
(fp_text reference R132 (at 5.08 -2.37) (layer F.SilkS)
Main: Summing design flaw fixed; better headphone vol. range - Multiple R and C value adaptions - Line Input: No relevant difference between INA134 and own circuit -> LM833 chosen - Signal busses/ summing module inputs fixed - TODO: On-Air Button - TODO: Update PCB layout
2020-12-13 21:02:02 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(fp_text value 390R (at 5.08 2.37) (layer F.Fab)
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(fp_line (start 1.93 -1.25) (end 1.93 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 1.93 1.25) (end 8.23 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 1.25) (end 8.23 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 -1.25) (end 1.93 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 0 0) (end 1.93 0) (layer F.Fab) (width 0.1))
(fp_line (start 10.16 0) (end 8.23 0) (layer F.Fab) (width 0.1))
(fp_line (start 1.81 -1.37) (end 1.81 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 1.81 1.37) (end 8.35 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 8.35 1.37) (end 8.35 -1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 8.35 -1.37) (end 1.81 -1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 1.04 0) (end 1.81 0) (layer F.SilkS) (width 0.12))
(fp_line (start 9.12 0) (end 8.35 0) (layer F.SilkS) (width 0.12))
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
(fp_line (start -1.05 -1.5) (end -1.05 1.5) (layer F.CrtYd) (width 0.05))
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(fp_line (start -1.05 1.5) (end 11.21 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 11.21 1.5) (end 11.21 -1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 11.21 -1.5) (end -1.05 -1.5) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 5.08 0) (layer F.Fab)
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(pad 2 thru_hole oval (at 10.16 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 62 "Net-(R132-Pad2)"))
(pad 1 thru_hole circle (at 0 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 35 "Net-(D117-Pad1)"))
(model ${KISYS3DMOD}/Resistor_THT.3dshapes/R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal.wrl
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(module Resistor_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal (layer F.Cu) (tedit 5AE5139B) (tstamp 60B1C850)
(at 87.63 62.23)
(descr "Resistor, Axial_DIN0207 series, Axial, Horizontal, pin pitch=10.16mm, 0.25W = 1/4W, length*diameter=6.3*2.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf")
(tags "Resistor Axial_DIN0207 series Axial Horizontal pin pitch 10.16mm 0.25W = 1/4W length 6.3mm diameter 2.5mm")
(path /60B42835)
(fp_text reference R131 (at 5.08 -2.37) (layer F.SilkS)
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(fp_text value 390R (at 5.08 2.37) (layer F.Fab)
Main: Summing design flaw fixed; better headphone vol. range - Multiple R and C value adaptions - Line Input: No relevant difference between INA134 and own circuit -> LM833 chosen - Signal busses/ summing module inputs fixed - TODO: On-Air Button - TODO: Update PCB layout
2020-12-13 21:02:02 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(fp_line (start 1.93 -1.25) (end 1.93 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 1.93 1.25) (end 8.23 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 1.25) (end 8.23 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 -1.25) (end 1.93 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 0 0) (end 1.93 0) (layer F.Fab) (width 0.1))
(fp_line (start 10.16 0) (end 8.23 0) (layer F.Fab) (width 0.1))
(fp_line (start 1.81 -1.37) (end 1.81 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 1.81 1.37) (end 8.35 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 8.35 1.37) (end 8.35 -1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 8.35 -1.37) (end 1.81 -1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 1.04 0) (end 1.81 0) (layer F.SilkS) (width 0.12))
(fp_line (start 9.12 0) (end 8.35 0) (layer F.SilkS) (width 0.12))
Main: Summing design flaw fixed; better headphone vol. range - Multiple R and C value adaptions - Line Input: No relevant difference between INA134 and own circuit -> LM833 chosen - Signal busses/ summing module inputs fixed - TODO: On-Air Button - TODO: Update PCB layout
2020-12-13 21:02:02 +00:00
(fp_line (start -1.05 -1.5) (end -1.05 1.5) (layer F.CrtYd) (width 0.05))
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(fp_line (start -1.05 1.5) (end 11.21 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 11.21 1.5) (end 11.21 -1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 11.21 -1.5) (end -1.05 -1.5) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 5.08 0) (layer F.Fab)
Main: Summing design flaw fixed; better headphone vol. range - Multiple R and C value adaptions - Line Input: No relevant difference between INA134 and own circuit -> LM833 chosen - Signal busses/ summing module inputs fixed - TODO: On-Air Button - TODO: Update PCB layout
2020-12-13 21:02:02 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(pad 2 thru_hole oval (at 10.16 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 61 "Net-(R131-Pad2)"))
(pad 1 thru_hole circle (at 0 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 34 "Net-(D116-Pad1)"))
(model ${KISYS3DMOD}/Resistor_THT.3dshapes/R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal.wrl
Schematic: Bugfixes, VU meter draft, first development PCB draft
2020-11-02 00:00:47 +00:00
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(module Resistor_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal (layer F.Cu) (tedit 5AE5139B) (tstamp 60B1C839)
(at 87.63 68.58)
(descr "Resistor, Axial_DIN0207 series, Axial, Horizontal, pin pitch=10.16mm, 0.25W = 1/4W, length*diameter=6.3*2.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf")
(tags "Resistor Axial_DIN0207 series Axial Horizontal pin pitch 10.16mm 0.25W = 1/4W length 6.3mm diameter 2.5mm")
(path /60B42846)
(fp_text reference R130 (at 5.08 -2.37) (layer F.SilkS)
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
(effects (font (size 1 1) (thickness 0.15)))
Schematic: Bugfixes, VU meter draft, first development PCB draft
2020-11-02 00:00:47 +00:00
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(fp_text value 390R (at 5.08 2.37) (layer F.Fab)
Schematic: Bugfixes, VU meter draft, first development PCB draft
2020-11-02 00:00:47 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(fp_line (start 1.93 -1.25) (end 1.93 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 1.93 1.25) (end 8.23 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 1.25) (end 8.23 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 -1.25) (end 1.93 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 0 0) (end 1.93 0) (layer F.Fab) (width 0.1))
(fp_line (start 10.16 0) (end 8.23 0) (layer F.Fab) (width 0.1))
(fp_line (start 1.81 -1.37) (end 1.81 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 1.81 1.37) (end 8.35 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 8.35 1.37) (end 8.35 -1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 8.35 -1.37) (end 1.81 -1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 1.04 0) (end 1.81 0) (layer F.SilkS) (width 0.12))
(fp_line (start 9.12 0) (end 8.35 0) (layer F.SilkS) (width 0.12))
(fp_line (start -1.05 -1.5) (end -1.05 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.5) (end 11.21 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 11.21 1.5) (end 11.21 -1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 11.21 -1.5) (end -1.05 -1.5) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 5.08 0) (layer F.Fab)
Schematic: Bugfixes, VU meter draft, first development PCB draft
2020-11-02 00:00:47 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(pad 2 thru_hole oval (at 10.16 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 60 "Net-(R130-Pad2)"))
(pad 1 thru_hole circle (at 0 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 33 "Net-(D115-Pad1)"))
(model ${KISYS3DMOD}/Resistor_THT.3dshapes/R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
Move VU-Meter to own project
2020-11-09 00:52:43 +00:00
)
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(module Resistor_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal (layer F.Cu) (tedit 5AE5139B) (tstamp 60B1C822)
(at 87.63 74.93)
(descr "Resistor, Axial_DIN0207 series, Axial, Horizontal, pin pitch=10.16mm, 0.25W = 1/4W, length*diameter=6.3*2.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf")
(tags "Resistor Axial_DIN0207 series Axial Horizontal pin pitch 10.16mm 0.25W = 1/4W length 6.3mm diameter 2.5mm")
(path /60B42857)
(fp_text reference R129 (at 5.08 -2.37) (layer F.SilkS)
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(fp_text value 390R (at 5.08 2.37) (layer F.Fab)
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
(effects (font (size 1 1) (thickness 0.15)))
Schematic: Bugfixes, VU meter draft, first development PCB draft
2020-11-02 00:00:47 +00:00
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(fp_line (start 1.93 -1.25) (end 1.93 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 1.93 1.25) (end 8.23 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 1.25) (end 8.23 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 -1.25) (end 1.93 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 0 0) (end 1.93 0) (layer F.Fab) (width 0.1))
(fp_line (start 10.16 0) (end 8.23 0) (layer F.Fab) (width 0.1))
(fp_line (start 1.81 -1.37) (end 1.81 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 1.81 1.37) (end 8.35 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 8.35 1.37) (end 8.35 -1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 8.35 -1.37) (end 1.81 -1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 1.04 0) (end 1.81 0) (layer F.SilkS) (width 0.12))
(fp_line (start 9.12 0) (end 8.35 0) (layer F.SilkS) (width 0.12))
(fp_line (start -1.05 -1.5) (end -1.05 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.5) (end 11.21 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 11.21 1.5) (end 11.21 -1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 11.21 -1.5) (end -1.05 -1.5) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 5.08 0) (layer F.Fab)
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(pad 2 thru_hole oval (at 10.16 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 59 "Net-(R129-Pad2)"))
(pad 1 thru_hole circle (at 0 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 32 "Net-(D114-Pad1)"))
(model ${KISYS3DMOD}/Resistor_THT.3dshapes/R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
Schematic: Bugfixes, VU meter draft, first development PCB draft
2020-11-02 00:00:47 +00:00
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(module Resistor_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal (layer F.Cu) (tedit 5AE5139B) (tstamp 60B1C80B)
(at 87.63 81.28)
(descr "Resistor, Axial_DIN0207 series, Axial, Horizontal, pin pitch=10.16mm, 0.25W = 1/4W, length*diameter=6.3*2.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf")
(tags "Resistor Axial_DIN0207 series Axial Horizontal pin pitch 10.16mm 0.25W = 1/4W length 6.3mm diameter 2.5mm")
(path /60B42868)
(fp_text reference R128 (at 5.08 -2.37) (layer F.SilkS)
Schematic: Bugfixes, VU meter draft, first development PCB draft
2020-11-02 00:00:47 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(fp_text value 390R (at 5.08 2.37) (layer F.Fab)
Schematic: Bugfixes, VU meter draft, first development PCB draft
2020-11-02 00:00:47 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(fp_line (start 1.93 -1.25) (end 1.93 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 1.93 1.25) (end 8.23 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 1.25) (end 8.23 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 -1.25) (end 1.93 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 0 0) (end 1.93 0) (layer F.Fab) (width 0.1))
(fp_line (start 10.16 0) (end 8.23 0) (layer F.Fab) (width 0.1))
(fp_line (start 1.81 -1.37) (end 1.81 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 1.81 1.37) (end 8.35 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 8.35 1.37) (end 8.35 -1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 8.35 -1.37) (end 1.81 -1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 1.04 0) (end 1.81 0) (layer F.SilkS) (width 0.12))
(fp_line (start 9.12 0) (end 8.35 0) (layer F.SilkS) (width 0.12))
(fp_line (start -1.05 -1.5) (end -1.05 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.5) (end 11.21 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 11.21 1.5) (end 11.21 -1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 11.21 -1.5) (end -1.05 -1.5) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 5.08 0) (layer F.Fab)
Schematic: Bugfixes, VU meter draft, first development PCB draft
2020-11-02 00:00:47 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(pad 2 thru_hole oval (at 10.16 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 58 "Net-(R128-Pad2)"))
(pad 1 thru_hole circle (at 0 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 31 "Net-(D113-Pad1)"))
(model ${KISYS3DMOD}/Resistor_THT.3dshapes/R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(module Resistor_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal (layer F.Cu) (tedit 5AE5139B) (tstamp 60B1C7F4)
(at 87.63 87.63)
(descr "Resistor, Axial_DIN0207 series, Axial, Horizontal, pin pitch=10.16mm, 0.25W = 1/4W, length*diameter=6.3*2.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf")
(tags "Resistor Axial_DIN0207 series Axial Horizontal pin pitch 10.16mm 0.25W = 1/4W length 6.3mm diameter 2.5mm")
(path /60B42879)
(fp_text reference R127 (at 5.08 -2.37) (layer F.SilkS)
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(fp_text value 390R (at 5.08 2.37) (layer F.Fab)
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(fp_line (start 1.93 -1.25) (end 1.93 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 1.93 1.25) (end 8.23 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 1.25) (end 8.23 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 -1.25) (end 1.93 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 0 0) (end 1.93 0) (layer F.Fab) (width 0.1))
(fp_line (start 10.16 0) (end 8.23 0) (layer F.Fab) (width 0.1))
(fp_line (start 1.81 -1.37) (end 1.81 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 1.81 1.37) (end 8.35 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 8.35 1.37) (end 8.35 -1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 8.35 -1.37) (end 1.81 -1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 1.04 0) (end 1.81 0) (layer F.SilkS) (width 0.12))
(fp_line (start 9.12 0) (end 8.35 0) (layer F.SilkS) (width 0.12))
(fp_line (start -1.05 -1.5) (end -1.05 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.5) (end 11.21 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 11.21 1.5) (end 11.21 -1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 11.21 -1.5) (end -1.05 -1.5) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 5.08 0) (layer F.Fab)
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(pad 2 thru_hole oval (at 10.16 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 57 "Net-(R127-Pad2)"))
(pad 1 thru_hole circle (at 0 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 30 "Net-(D112-Pad1)"))
(model ${KISYS3DMOD}/Resistor_THT.3dshapes/R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(module Resistor_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal (layer F.Cu) (tedit 5AE5139B) (tstamp 60B1C7DD)
(at 87.63 93.98)
(descr "Resistor, Axial_DIN0207 series, Axial, Horizontal, pin pitch=10.16mm, 0.25W = 1/4W, length*diameter=6.3*2.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf")
(tags "Resistor Axial_DIN0207 series Axial Horizontal pin pitch 10.16mm 0.25W = 1/4W length 6.3mm diameter 2.5mm")
(path /60B4288A)
(fp_text reference R126 (at 5.08 -2.37) (layer F.SilkS)
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(fp_text value 390R (at 5.08 2.37) (layer F.Fab)
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(fp_line (start 1.93 -1.25) (end 1.93 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 1.93 1.25) (end 8.23 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 1.25) (end 8.23 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 -1.25) (end 1.93 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 0 0) (end 1.93 0) (layer F.Fab) (width 0.1))
(fp_line (start 10.16 0) (end 8.23 0) (layer F.Fab) (width 0.1))
(fp_line (start 1.81 -1.37) (end 1.81 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 1.81 1.37) (end 8.35 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 8.35 1.37) (end 8.35 -1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 8.35 -1.37) (end 1.81 -1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 1.04 0) (end 1.81 0) (layer F.SilkS) (width 0.12))
(fp_line (start 9.12 0) (end 8.35 0) (layer F.SilkS) (width 0.12))
(fp_line (start -1.05 -1.5) (end -1.05 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.5) (end 11.21 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 11.21 1.5) (end 11.21 -1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 11.21 -1.5) (end -1.05 -1.5) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 5.08 0) (layer F.Fab)
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(pad 2 thru_hole oval (at 10.16 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 56 "Net-(R126-Pad2)"))
(pad 1 thru_hole circle (at 0 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 29 "Net-(D111-Pad1)"))
(model ${KISYS3DMOD}/Resistor_THT.3dshapes/R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(module Resistor_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal (layer F.Cu) (tedit 5AE5139B) (tstamp 60B1C7C6)
(at 87.63 100.33)
(descr "Resistor, Axial_DIN0207 series, Axial, Horizontal, pin pitch=10.16mm, 0.25W = 1/4W, length*diameter=6.3*2.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf")
(tags "Resistor Axial_DIN0207 series Axial Horizontal pin pitch 10.16mm 0.25W = 1/4W length 6.3mm diameter 2.5mm")
(path /60B4289B)
(fp_text reference R125 (at 5.08 -2.37) (layer F.SilkS)
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(fp_text value 390R (at 5.08 2.37) (layer F.Fab)
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(fp_line (start 1.93 -1.25) (end 1.93 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 1.93 1.25) (end 8.23 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 1.25) (end 8.23 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 -1.25) (end 1.93 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 0 0) (end 1.93 0) (layer F.Fab) (width 0.1))
(fp_line (start 10.16 0) (end 8.23 0) (layer F.Fab) (width 0.1))
(fp_line (start 1.81 -1.37) (end 1.81 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 1.81 1.37) (end 8.35 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 8.35 1.37) (end 8.35 -1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 8.35 -1.37) (end 1.81 -1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 1.04 0) (end 1.81 0) (layer F.SilkS) (width 0.12))
(fp_line (start 9.12 0) (end 8.35 0) (layer F.SilkS) (width 0.12))
(fp_line (start -1.05 -1.5) (end -1.05 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.5) (end 11.21 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 11.21 1.5) (end 11.21 -1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 11.21 -1.5) (end -1.05 -1.5) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 5.08 0) (layer F.Fab)
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(pad 2 thru_hole oval (at 10.16 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 55 "Net-(R125-Pad2)"))
(pad 1 thru_hole circle (at 0 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 28 "Net-(D110-Pad1)"))
(model ${KISYS3DMOD}/Resistor_THT.3dshapes/R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(module Resistor_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal (layer F.Cu) (tedit 5AE5139B) (tstamp 60B1C7AF)
(at 87.63 106.68)
(descr "Resistor, Axial_DIN0207 series, Axial, Horizontal, pin pitch=10.16mm, 0.25W = 1/4W, length*diameter=6.3*2.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf")
(tags "Resistor Axial_DIN0207 series Axial Horizontal pin pitch 10.16mm 0.25W = 1/4W length 6.3mm diameter 2.5mm")
(path /60B428AC)
(fp_text reference R124 (at 5.08 -2.37) (layer F.SilkS)
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(fp_text value 390R (at 5.08 2.37) (layer F.Fab)
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(fp_line (start 1.93 -1.25) (end 1.93 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 1.93 1.25) (end 8.23 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 1.25) (end 8.23 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 -1.25) (end 1.93 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 0 0) (end 1.93 0) (layer F.Fab) (width 0.1))
(fp_line (start 10.16 0) (end 8.23 0) (layer F.Fab) (width 0.1))
(fp_line (start 1.81 -1.37) (end 1.81 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 1.81 1.37) (end 8.35 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 8.35 1.37) (end 8.35 -1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 8.35 -1.37) (end 1.81 -1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 1.04 0) (end 1.81 0) (layer F.SilkS) (width 0.12))
(fp_line (start 9.12 0) (end 8.35 0) (layer F.SilkS) (width 0.12))
(fp_line (start -1.05 -1.5) (end -1.05 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.5) (end 11.21 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 11.21 1.5) (end 11.21 -1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 11.21 -1.5) (end -1.05 -1.5) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 5.08 0) (layer F.Fab)
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(pad 2 thru_hole oval (at 10.16 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 54 "Net-(R124-Pad2)"))
(pad 1 thru_hole circle (at 0 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 27 "Net-(D109-Pad1)"))
(model ${KISYS3DMOD}/Resistor_THT.3dshapes/R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(module Resistor_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal (layer F.Cu) (tedit 5AE5139B) (tstamp 60B1C798)
(at 87.63 113.03)
(descr "Resistor, Axial_DIN0207 series, Axial, Horizontal, pin pitch=10.16mm, 0.25W = 1/4W, length*diameter=6.3*2.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf")
(tags "Resistor Axial_DIN0207 series Axial Horizontal pin pitch 10.16mm 0.25W = 1/4W length 6.3mm diameter 2.5mm")
(path /60B428BD)
(fp_text reference R123 (at 5.08 -2.37) (layer F.SilkS)
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(fp_text value 390R (at 5.08 2.37) (layer F.Fab)
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(fp_line (start 1.93 -1.25) (end 1.93 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 1.93 1.25) (end 8.23 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 1.25) (end 8.23 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 -1.25) (end 1.93 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 0 0) (end 1.93 0) (layer F.Fab) (width 0.1))
(fp_line (start 10.16 0) (end 8.23 0) (layer F.Fab) (width 0.1))
(fp_line (start 1.81 -1.37) (end 1.81 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 1.81 1.37) (end 8.35 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 8.35 1.37) (end 8.35 -1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 8.35 -1.37) (end 1.81 -1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 1.04 0) (end 1.81 0) (layer F.SilkS) (width 0.12))
(fp_line (start 9.12 0) (end 8.35 0) (layer F.SilkS) (width 0.12))
(fp_line (start -1.05 -1.5) (end -1.05 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.5) (end 11.21 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 11.21 1.5) (end 11.21 -1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 11.21 -1.5) (end -1.05 -1.5) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 5.08 0) (layer F.Fab)
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(pad 2 thru_hole oval (at 10.16 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 53 "Net-(R123-Pad2)"))
(pad 1 thru_hole circle (at 0 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 26 "Net-(D108-Pad1)"))
(model ${KISYS3DMOD}/Resistor_THT.3dshapes/R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(module Resistor_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal (layer F.Cu) (tedit 5AE5139B) (tstamp 60B1C781)
(at 87.63 119.38)
(descr "Resistor, Axial_DIN0207 series, Axial, Horizontal, pin pitch=10.16mm, 0.25W = 1/4W, length*diameter=6.3*2.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf")
(tags "Resistor Axial_DIN0207 series Axial Horizontal pin pitch 10.16mm 0.25W = 1/4W length 6.3mm diameter 2.5mm")
(path /60B428CE)
(fp_text reference R122 (at 5.08 -2.37) (layer F.SilkS)
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(fp_text value 390R (at 5.08 2.37) (layer F.Fab)
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(fp_line (start 1.93 -1.25) (end 1.93 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 1.93 1.25) (end 8.23 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 1.25) (end 8.23 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 -1.25) (end 1.93 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 0 0) (end 1.93 0) (layer F.Fab) (width 0.1))
(fp_line (start 10.16 0) (end 8.23 0) (layer F.Fab) (width 0.1))
(fp_line (start 1.81 -1.37) (end 1.81 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 1.81 1.37) (end 8.35 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 8.35 1.37) (end 8.35 -1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 8.35 -1.37) (end 1.81 -1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 1.04 0) (end 1.81 0) (layer F.SilkS) (width 0.12))
(fp_line (start 9.12 0) (end 8.35 0) (layer F.SilkS) (width 0.12))
(fp_line (start -1.05 -1.5) (end -1.05 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.5) (end 11.21 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 11.21 1.5) (end 11.21 -1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 11.21 -1.5) (end -1.05 -1.5) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 5.08 0) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 2 thru_hole oval (at 10.16 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 52 "Net-(R122-Pad2)"))
(pad 1 thru_hole circle (at 0 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 25 "Net-(D107-Pad1)"))
(model ${KISYS3DMOD}/Resistor_THT.3dshapes/R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal.wrl
Schematic: Bugfixes, VU meter draft, first development PCB draft
2020-11-02 00:00:47 +00:00
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(module Resistor_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal (layer F.Cu) (tedit 5AE5139B) (tstamp 60B1C76A)
(at 87.63 125.73)
(descr "Resistor, Axial_DIN0207 series, Axial, Horizontal, pin pitch=10.16mm, 0.25W = 1/4W, length*diameter=6.3*2.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf")
(tags "Resistor Axial_DIN0207 series Axial Horizontal pin pitch 10.16mm 0.25W = 1/4W length 6.3mm diameter 2.5mm")
(path /60B428DF)
(fp_text reference R121 (at 5.08 -2.37) (layer F.SilkS)
Schematic: Bugfixes, VU meter draft, first development PCB draft
2020-11-02 00:00:47 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(fp_text value 390R (at 5.08 2.37) (layer F.Fab)
Schematic: Bugfixes, VU meter draft, first development PCB draft
2020-11-02 00:00:47 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(fp_line (start 1.93 -1.25) (end 1.93 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 1.93 1.25) (end 8.23 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 1.25) (end 8.23 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 -1.25) (end 1.93 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 0 0) (end 1.93 0) (layer F.Fab) (width 0.1))
(fp_line (start 10.16 0) (end 8.23 0) (layer F.Fab) (width 0.1))
(fp_line (start 1.81 -1.37) (end 1.81 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 1.81 1.37) (end 8.35 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 8.35 1.37) (end 8.35 -1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 8.35 -1.37) (end 1.81 -1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 1.04 0) (end 1.81 0) (layer F.SilkS) (width 0.12))
(fp_line (start 9.12 0) (end 8.35 0) (layer F.SilkS) (width 0.12))
(fp_line (start -1.05 -1.5) (end -1.05 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.5) (end 11.21 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 11.21 1.5) (end 11.21 -1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 11.21 -1.5) (end -1.05 -1.5) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 5.08 0) (layer F.Fab)
Schematic: Bugfixes, VU meter draft, first development PCB draft
2020-11-02 00:00:47 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(pad 2 thru_hole oval (at 10.16 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 51 "Net-(R121-Pad2)"))
(pad 1 thru_hole circle (at 0 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 24 "Net-(D106-Pad1)"))
(model ${KISYS3DMOD}/Resistor_THT.3dshapes/R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal.wrl
Schematic: Bugfixes, VU meter draft, first development PCB draft
2020-11-02 00:00:47 +00:00
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(module Resistor_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal (layer F.Cu) (tedit 5AE5139B) (tstamp 60B1C753)
(at 97.79 138.43)
(descr "Resistor, Axial_DIN0207 series, Axial, Horizontal, pin pitch=10.16mm, 0.25W = 1/4W, length*diameter=6.3*2.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf")
(tags "Resistor Axial_DIN0207 series Axial Horizontal pin pitch 10.16mm 0.25W = 1/4W length 6.3mm diameter 2.5mm")
(path /60B42949)
(fp_text reference R120 (at 5.08 -2.37) (layer F.SilkS)
Schematic: Bugfixes, VU meter draft, first development PCB draft
2020-11-02 00:00:47 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(fp_text value 3.9K (at 5.08 2.37) (layer F.Fab)
Schematic: Bugfixes, VU meter draft, first development PCB draft
2020-11-02 00:00:47 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(fp_line (start 1.93 -1.25) (end 1.93 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 1.93 1.25) (end 8.23 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 1.25) (end 8.23 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 -1.25) (end 1.93 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 0 0) (end 1.93 0) (layer F.Fab) (width 0.1))
(fp_line (start 10.16 0) (end 8.23 0) (layer F.Fab) (width 0.1))
(fp_line (start 1.81 -1.37) (end 1.81 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 1.81 1.37) (end 8.35 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 8.35 1.37) (end 8.35 -1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 8.35 -1.37) (end 1.81 -1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 1.04 0) (end 1.81 0) (layer F.SilkS) (width 0.12))
(fp_line (start 9.12 0) (end 8.35 0) (layer F.SilkS) (width 0.12))
(fp_line (start -1.05 -1.5) (end -1.05 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.5) (end 11.21 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 11.21 1.5) (end 11.21 -1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 11.21 -1.5) (end -1.05 -1.5) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 5.08 0) (layer F.Fab)
Schematic: Bugfixes, VU meter draft, first development PCB draft
2020-11-02 00:00:47 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(pad 2 thru_hole oval (at 10.16 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 36 "Net-(D118-Pad2)"))
(pad 1 thru_hole circle (at 0 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 20 "Net-(C120-Pad1)"))
(model ${KISYS3DMOD}/Resistor_THT.3dshapes/R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal.wrl
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
(at (xyz 0 0 0))
Schematic: Bugfixes, VU meter draft, first development PCB draft
2020-11-02 00:00:47 +00:00
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(module Resistor_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal (layer F.Cu) (tedit 5AE5139B) (tstamp 60B1C61E)
(at 53.34 60.96)
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
(descr "Resistor, Axial_DIN0207 series, Axial, Horizontal, pin pitch=10.16mm, 0.25W = 1/4W, length*diameter=6.3*2.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf")
(tags "Resistor Axial_DIN0207 series Axial Horizontal pin pitch 10.16mm 0.25W = 1/4W length 6.3mm diameter 2.5mm")
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(path /60DE75B7)
(fp_text reference R106 (at 5.08 -2.37) (layer F.SilkS)
Schematic: Bugfixes, VU meter draft, first development PCB draft
2020-11-02 00:00:47 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(fp_text value 390R (at 5.08 2.37) (layer F.Fab)
Schematic: Bugfixes, VU meter draft, first development PCB draft
2020-11-02 00:00:47 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
(fp_line (start 1.93 -1.25) (end 1.93 1.25) (layer F.Fab) (width 0.1))
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(fp_line (start 1.93 1.25) (end 8.23 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 1.25) (end 8.23 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 -1.25) (end 1.93 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 0 0) (end 1.93 0) (layer F.Fab) (width 0.1))
(fp_line (start 10.16 0) (end 8.23 0) (layer F.Fab) (width 0.1))
(fp_line (start 1.81 -1.37) (end 1.81 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 1.81 1.37) (end 8.35 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 8.35 1.37) (end 8.35 -1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 8.35 -1.37) (end 1.81 -1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 1.04 0) (end 1.81 0) (layer F.SilkS) (width 0.12))
(fp_line (start 9.12 0) (end 8.35 0) (layer F.SilkS) (width 0.12))
(fp_line (start -1.05 -1.5) (end -1.05 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.5) (end 11.21 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 11.21 1.5) (end 11.21 -1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 11.21 -1.5) (end -1.05 -1.5) (layer F.CrtYd) (width 0.05))
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
(fp_text user %R (at 5.08 0) (layer F.Fab)
Schematic: Bugfixes, VU meter draft, first development PCB draft
2020-11-02 00:00:47 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
(pad 2 thru_hole oval (at 10.16 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(net 3 GND))
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
(pad 1 thru_hole circle (at 0 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(net 22 "Net-(D101-Pad1)"))
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
(model ${KISYS3DMOD}/Resistor_THT.3dshapes/R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal.wrl
Schematic: Bugfixes, VU meter draft, first development PCB draft
2020-11-02 00:00:47 +00:00
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(module Jumper:SolderJumper-2_P1.3mm_Open_TrianglePad1.0x1.5mm (layer B.Cu) (tedit 5A64794F) (tstamp 60B1C599)
(at 76.2 217.79 270)
(descr "SMD Solder Jumper, 1x1.5mm Triangular Pads, 0.3mm gap, open")
(tags "solder jumper open")
(path /612142A6)
(attr virtual)
(fp_text reference JP102 (at 0 1.8 90) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value GND_JMP (at 0 -1.9 90) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_line (start -1.4 -1) (end -1.4 1) (layer B.SilkS) (width 0.12))
(fp_line (start 1.4 -1) (end -1.4 -1) (layer B.SilkS) (width 0.12))
(fp_line (start 1.4 1) (end 1.4 -1) (layer B.SilkS) (width 0.12))
(fp_line (start -1.4 1) (end 1.4 1) (layer B.SilkS) (width 0.12))
(fp_line (start -1.65 1.25) (end 1.65 1.25) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.65 1.25) (end -1.65 -1.25) (layer B.CrtYd) (width 0.05))
(fp_line (start 1.65 -1.25) (end 1.65 1.25) (layer B.CrtYd) (width 0.05))
(fp_line (start 1.65 -1.25) (end -1.65 -1.25) (layer B.CrtYd) (width 0.05))
(pad 1 smd custom (at -0.725 0 270) (size 0.3 0.3) (layers B.Cu B.Mask)
(net 3 GND) (zone_connect 2)
(options (clearance outline) (anchor rect))
(primitives
(gr_poly (pts
(xy -0.5 0.75) (xy 0.5 0.75) (xy 1 0) (xy 0.5 -0.75) (xy -0.5 -0.75)
) (width 0))
))
(pad 2 smd custom (at 0.725 0 270) (size 0.3 0.3) (layers B.Cu B.Mask)
(net 38 GNDREF) (zone_connect 2)
(options (clearance outline) (anchor rect))
(primitives
(gr_poly (pts
(xy -0.65 0.75) (xy 0.5 0.75) (xy 0.5 -0.75) (xy -0.65 -0.75) (xy -0.15 0)
) (width 0))
))
)
(module Connector_Audio:Jack_6.35mm_Neutrik_NMJ6HFD2_Horizontal locked (layer F.Cu) (tedit 5C194A25) (tstamp 5F9EF16A)
(at 100 216 270)
(descr "M Series, 6.35mm (1/4in) stereo jack, switched, with full threaded nose and straight PCB pins, https://www.neutrik.com/en/product/nmj6hfd2")
(tags "neutrik jack m")
(path /5F821533)
(fp_text reference J102 (at 6.35 -3 90) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value "Headphone X" (at 6.35 19 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -7.45 18.23) (end 26.4 18.23) (layer F.CrtYd) (width 0.05))
(fp_line (start 26.4 18.23) (end 26.4 -2) (layer F.CrtYd) (width 0.05))
(fp_line (start 26.4 -2) (end -7.45 -2) (layer F.CrtYd) (width 0.05))
(fp_line (start -7.45 18.23) (end -7.45 -2) (layer F.CrtYd) (width 0.05))
(fp_line (start 17.17 2.495) (end 26.02 2.495) (layer F.SilkS) (width 0.12))
(fp_line (start 26.02 13.735) (end 26.02 2.495) (layer F.SilkS) (width 0.12))
(fp_line (start 17.17 13.735) (end 26.02 13.735) (layer F.SilkS) (width 0.12))
(fp_line (start -7.07 12.585) (end -4.07 12.585) (layer F.SilkS) (width 0.12))
(fp_line (start 17.17 17.335) (end 17.17 13.735) (layer F.SilkS) (width 0.12))
(fp_line (start 17.17 -1.105) (end 14.05 -1.105) (layer F.SilkS) (width 0.12))
(fp_line (start 17.17 17.335) (end 14.05 17.335) (layer F.SilkS) (width 0.12))
(fp_line (start -1.35 17.335) (end -4.07 17.335) (layer F.SilkS) (width 0.12))
(fp_line (start 5 17.335) (end 1.4 17.335) (layer F.SilkS) (width 0.12))
(fp_line (start 11.3 17.335) (end 7.7 17.335) (layer F.SilkS) (width 0.12))
(fp_line (start 7.7 -1.105) (end 11.3 -1.105) (layer F.SilkS) (width 0.12))
(fp_line (start 1.4 -1.105) (end 5 -1.105) (layer F.SilkS) (width 0.12))
(fp_line (start -4.07 -1.105) (end -1.35 -1.105) (layer F.SilkS) (width 0.12))
(fp_line (start -4.07 17.335) (end -4.07 12.585) (layer F.SilkS) (width 0.12))
(fp_line (start 17.05 17.215) (end -3.95 17.215) (layer F.Fab) (width 0.1))
(fp_line (start 17.05 17.215) (end 17.05 -0.985) (layer F.Fab) (width 0.1))
(fp_line (start 17.05 -0.985) (end -3.95 -0.985) (layer F.Fab) (width 0.1))
(fp_line (start -6.95 12.465) (end -6.95 3.765) (layer F.Fab) (width 0.1))
(fp_line (start -3.95 17.215) (end -3.95 -0.985) (layer F.Fab) (width 0.1))
(fp_line (start 25.9 13.615) (end 25.9 2.615) (layer F.Fab) (width 0.1))
(fp_line (start 25.9 13.615) (end 17.05 13.615) (layer F.Fab) (width 0.1))
(fp_line (start 25.9 2.615) (end 17.05 2.615) (layer F.Fab) (width 0.1))
(fp_line (start -6.95 12.465) (end -3.95 12.465) (layer F.Fab) (width 0.1))
(fp_line (start -6.95 3.765) (end -3.95 3.765) (layer F.Fab) (width 0.1))
(fp_line (start -7.07 12.545) (end -7.07 3.645) (layer F.SilkS) (width 0.12))
(fp_line (start -7.07 3.645) (end -4.07 3.645) (layer F.SilkS) (width 0.12))
(fp_line (start -4.07 3.645) (end -4.07 -1.105) (layer F.SilkS) (width 0.12))
(fp_line (start 17.17 2.495) (end 17.17 -1.105) (layer F.SilkS) (width 0.12))
(fp_text user %R (at 6.35 8.115 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad TN thru_hole circle (at 0 16.23 270) (size 3 3) (drill 1.4) (layers *.Cu *.Mask))
(pad SN thru_hole circle (at 12.7 16.23 270) (size 3 3) (drill 1.4) (layers *.Cu *.Mask))
(pad RN thru_hole circle (at 6.35 16.23 270) (size 3 3) (drill 1.4) (layers *.Cu *.Mask))
(pad T thru_hole circle (at 0 0 270) (size 3 3) (drill 1.4) (layers *.Cu *.Mask)
(net 10 "Net-(C110-Pad2)"))
(pad S thru_hole circle (at 12.7 0 270) (size 3 3) (drill 1.4) (layers *.Cu *.Mask)
(net 3 GND))
(pad R thru_hole circle (at 6.35 0 270) (size 3 3) (drill 1.4) (layers *.Cu *.Mask)
(net 10 "Net-(C110-Pad2)"))
(model ${KISYS3DMOD}/Connector_Audio.3dshapes/Jack_6.35mm_Neutrik_NMJ6HFD2_Horizontal.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Connector_Audio:Jack_XLR_Neutrik_NC3FAAH2_Horizontal locked (layer F.Cu) (tedit 5E6942D2) (tstamp 5F9EF181)
(at 68.81 220.45 270)
(descr "AA Series, 3 pole female XLR receptacle, grounding: separate ground contact to mating connector shell and front panel, horizontal PCB mount, https://www.neutrik.com/en/product/nc3faah2")
(tags "neutrik xlr aa")
(path /5F81A769)
(fp_text reference J101 (at 4.3 -10 90) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value "Mic X In" (at 4.3 17.5 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 15.4 14.81) (end 12.7 14.81) (layer F.Fab) (width 0.1))
(fp_line (start 15.4 -7.19) (end 15.4 14.81) (layer F.Fab) (width 0.1))
(fp_line (start 12.7 -7.19) (end 15.4 -7.19) (layer F.Fab) (width 0.1))
(fp_line (start 6.2 -8.69) (end 12.7 -8.69) (layer F.Fab) (width 0.1))
(fp_line (start 6.2 16.31) (end 6.2 -8.69) (layer F.Fab) (width 0.1))
(fp_line (start 12.7 16.31) (end 6.2 16.31) (layer F.Fab) (width 0.1))
(fp_line (start 12.7 -8.69) (end 12.7 16.31) (layer F.Fab) (width 0.1))
(fp_line (start 12.7 -8.69) (end 12.7 16.31) (layer Dwgs.User) (width 0.1))
(fp_line (start 12.82 16.43) (end 6.08 16.43) (layer F.SilkS) (width 0.12))
(fp_line (start 12.82 -8.81) (end 6.08 -8.81) (layer F.SilkS) (width 0.12))
(fp_line (start 6.08 -7.06) (end 6.08 -8.81) (layer F.SilkS) (width 0.12))
(fp_line (start 6.08 16.43) (end 6.08 14.68) (layer F.SilkS) (width 0.12))
(fp_line (start 12.82 -7.31) (end 15.52 -7.31) (layer F.SilkS) (width 0.12))
(fp_line (start 12.82 14.93) (end 15.52 14.93) (layer F.SilkS) (width 0.12))
(fp_line (start 12.82 14.93) (end 12.82 16.43) (layer F.SilkS) (width 0.12))
(fp_line (start 12.82 -8.81) (end 12.82 -7.31) (layer F.SilkS) (width 0.12))
(fp_line (start 15.52 -7.31) (end 15.52 14.93) (layer F.SilkS) (width 0.12))
(fp_line (start 15.9 16.81) (end -7.3 16.81) (layer F.CrtYd) (width 0.05))
(fp_line (start 15.9 -9.19) (end -7.3 -9.19) (layer F.CrtYd) (width 0.05))
(fp_line (start -7.3 -9.19) (end -7.3 16.81) (layer F.CrtYd) (width 0.05))
(fp_line (start 15.9 -9.19) (end 15.9 16.81) (layer F.CrtYd) (width 0.05))
(fp_line (start 0.58 11.93) (end -6.92 11.93) (layer F.SilkS) (width 0.12))
(fp_line (start 0.7 -6.94) (end 0.7 14.56) (layer F.Fab) (width 0.1))
(fp_line (start -6.92 -4.31) (end -6.92 11.93) (layer F.SilkS) (width 0.12))
(fp_line (start -6.8 11.81) (end 0.7 11.81) (layer F.Fab) (width 0.1))
(fp_line (start 6.08 -7.06) (end 0.58 -7.06) (layer F.SilkS) (width 0.12))
(fp_line (start -6.8 -4.19) (end -6.8 11.81) (layer F.Fab) (width 0.1))
(fp_line (start 0.58 -4.31) (end -6.92 -4.31) (layer F.SilkS) (width 0.12))
(fp_line (start 0.7 -4.19) (end -6.8 -4.19) (layer F.Fab) (width 0.1))
(fp_line (start 0.58 11.93) (end 0.58 14.68) (layer F.SilkS) (width 0.12))
(fp_line (start 6.08 14.68) (end 0.58 14.68) (layer F.SilkS) (width 0.12))
(fp_line (start 6.2 -6.94) (end 0.7 -6.94) (layer F.Fab) (width 0.1))
(fp_line (start 0.7 14.56) (end 6.2 14.56) (layer F.Fab) (width 0.1))
(fp_line (start 0.58 -7.06) (end 0.58 -4.31) (layer F.SilkS) (width 0.12))
(fp_text user %R (at 10.35 3.81 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad G thru_hole circle (at 5.72 -4.44 270) (size 2.9 2.9) (drill 1.2) (layers *.Cu *.Mask)
(net 38 GNDREF))
(pad "" np_thru_hole circle (at 3.81 7.62 270) (size 1.6 1.6) (drill 1.6) (layers *.Cu *.Mask))
(pad "" np_thru_hole circle (at 8.89 0 270) (size 1.6 1.6) (drill 1.6) (layers *.Cu *.Mask))
(pad 3 thru_hole circle (at -4.45 3.81 270) (size 2.9 2.9) (drill 1.2) (layers *.Cu *.Mask)
(net 15 "Net-(C113-Pad1)"))
(pad 2 thru_hole circle (at -0.635 7.62 270) (size 3.4 3.4) (drill 1.6) (layers *.Cu *.Mask)
(net 7 "Net-(C107-Pad1)"))
(pad 1 thru_hole circle (at 0 0 270) (size 3.4 3.4) (drill 1.6) (layers *.Cu *.Mask)
(net 3 GND))
(model ${KISYS3DMOD}/Connector_Audio.3dshapes/Jack_XLR_Neutrik_NC3FAAH2_Horizontal.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Diode_THT:D_DO-35_SOD27_P10.16mm_Horizontal (layer F.Cu) (tedit 5AE50CD5) (tstamp 60B1C495)
(at 111.76 133.35 270)
(descr "Diode, DO-35_SOD27 series, Axial, Horizontal, pin pitch=10.16mm, , length*diameter=4*2mm^2, , http://www.diodes.com/_files/packages/DO-35.pdf")
(tags "Diode DO-35_SOD27 series Axial Horizontal pin pitch 10.16mm length 4mm diameter 2mm")
(path /60B4295B)
(fp_text reference D118 (at 5.08 -2.12 90) (layer F.SilkS)
Schematic: Bugfixes, VU meter draft, first development PCB draft
2020-11-02 00:00:47 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(fp_text value 1N4148 (at 5.08 2.12 90) (layer F.Fab)
Schematic: Bugfixes, VU meter draft, first development PCB draft
2020-11-02 00:00:47 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(fp_line (start 3.08 -1) (end 3.08 1) (layer F.Fab) (width 0.1))
(fp_line (start 3.08 1) (end 7.08 1) (layer F.Fab) (width 0.1))
(fp_line (start 7.08 1) (end 7.08 -1) (layer F.Fab) (width 0.1))
(fp_line (start 7.08 -1) (end 3.08 -1) (layer F.Fab) (width 0.1))
(fp_line (start 0 0) (end 3.08 0) (layer F.Fab) (width 0.1))
(fp_line (start 10.16 0) (end 7.08 0) (layer F.Fab) (width 0.1))
(fp_line (start 3.68 -1) (end 3.68 1) (layer F.Fab) (width 0.1))
(fp_line (start 3.78 -1) (end 3.78 1) (layer F.Fab) (width 0.1))
(fp_line (start 3.58 -1) (end 3.58 1) (layer F.Fab) (width 0.1))
(fp_line (start 2.96 -1.12) (end 2.96 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 2.96 1.12) (end 7.2 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 7.2 1.12) (end 7.2 -1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 7.2 -1.12) (end 2.96 -1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 1.04 0) (end 2.96 0) (layer F.SilkS) (width 0.12))
(fp_line (start 9.12 0) (end 7.2 0) (layer F.SilkS) (width 0.12))
(fp_line (start 3.68 -1.12) (end 3.68 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 3.8 -1.12) (end 3.8 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 3.56 -1.12) (end 3.56 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start -1.05 -1.25) (end -1.05 1.25) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.25) (end 11.21 1.25) (layer F.CrtYd) (width 0.05))
(fp_line (start 11.21 1.25) (end 11.21 -1.25) (layer F.CrtYd) (width 0.05))
(fp_line (start 11.21 -1.25) (end -1.05 -1.25) (layer F.CrtYd) (width 0.05))
(fp_text user K (at 0 -1.8 90) (layer F.SilkS)
Schematic: Bugfixes, VU meter draft, first development PCB draft
2020-11-02 00:00:47 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(fp_text user K (at 0 -1.8 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 5.38 0 90) (layer F.Fab)
(effects (font (size 0.8 0.8) (thickness 0.12)))
)
(pad 2 thru_hole oval (at 10.16 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 36 "Net-(D118-Pad2)"))
(pad 1 thru_hole rect (at 0 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 37 "Net-(D118-Pad1)"))
(model ${KISYS3DMOD}/Diode_THT.3dshapes/D_DO-35_SOD27_P10.16mm_Horizontal.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module LED_THT:LED_D5.0mm locked (layer F.Cu) (tedit 5995936A) (tstamp 60B1C476)
(at 83 56.54 90)
(descr "LED, diameter 5.0mm, 2 pins, http://cdn-reichelt.de/documents/datenblatt/A500/LL-504BC2E-009.pdf")
(tags "LED diameter 5.0mm 2 pins")
(path /60B4282C)
(fp_text reference D117 (at 1.27 -3.96 90) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value rd (at 1.27 3.96 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_circle (center 1.27 0) (end 3.77 0) (layer F.Fab) (width 0.1))
(fp_circle (center 1.27 0) (end 3.77 0) (layer F.SilkS) (width 0.12))
(fp_line (start -1.23 -1.469694) (end -1.23 1.469694) (layer F.Fab) (width 0.1))
(fp_line (start -1.29 -1.545) (end -1.29 1.545) (layer F.SilkS) (width 0.12))
(fp_line (start -1.95 -3.25) (end -1.95 3.25) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.95 3.25) (end 4.5 3.25) (layer F.CrtYd) (width 0.05))
(fp_line (start 4.5 3.25) (end 4.5 -3.25) (layer F.CrtYd) (width 0.05))
(fp_line (start 4.5 -3.25) (end -1.95 -3.25) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 1.25 0 90) (layer F.Fab)
(effects (font (size 0.8 0.8) (thickness 0.2)))
)
(fp_arc (start 1.27 0) (end -1.29 1.54483) (angle -148.9) (layer F.SilkS) (width 0.12))
(fp_arc (start 1.27 0) (end -1.29 -1.54483) (angle 148.9) (layer F.SilkS) (width 0.12))
(fp_arc (start 1.27 0) (end -1.23 -1.469694) (angle 299.1) (layer F.Fab) (width 0.1))
(pad 2 thru_hole circle (at 2.54 0 90) (size 1.8 1.8) (drill 0.9) (layers *.Cu *.Mask)
(net 23 V_LED))
(pad 1 thru_hole rect (at 0 0 90) (size 1.8 1.8) (drill 0.9) (layers *.Cu *.Mask)
(net 35 "Net-(D117-Pad1)"))
(model ${KISYS3DMOD}/LED_THT.3dshapes/LED_D5.0mm.wrl
Schematic: Bugfixes, VU meter draft, first development PCB draft
2020-11-02 00:00:47 +00:00
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(module LED_THT:LED_D5.0mm locked (layer F.Cu) (tedit 5995936A) (tstamp 60B1C464)
(at 83 63.04 90)
(descr "LED, diameter 5.0mm, 2 pins, http://cdn-reichelt.de/documents/datenblatt/A500/LL-504BC2E-009.pdf")
(tags "LED diameter 5.0mm 2 pins")
(path /60B4283C)
(fp_text reference D116 (at 1.27 -3.96 90) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value ye (at 1.27 3.96 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_circle (center 1.27 0) (end 3.77 0) (layer F.Fab) (width 0.1))
(fp_circle (center 1.27 0) (end 3.77 0) (layer F.SilkS) (width 0.12))
(fp_line (start -1.23 -1.469694) (end -1.23 1.469694) (layer F.Fab) (width 0.1))
(fp_line (start -1.29 -1.545) (end -1.29 1.545) (layer F.SilkS) (width 0.12))
(fp_line (start -1.95 -3.25) (end -1.95 3.25) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.95 3.25) (end 4.5 3.25) (layer F.CrtYd) (width 0.05))
(fp_line (start 4.5 3.25) (end 4.5 -3.25) (layer F.CrtYd) (width 0.05))
(fp_line (start 4.5 -3.25) (end -1.95 -3.25) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 1.25 0 90) (layer F.Fab)
(effects (font (size 0.8 0.8) (thickness 0.2)))
)
(fp_arc (start 1.27 0) (end -1.29 1.54483) (angle -148.9) (layer F.SilkS) (width 0.12))
(fp_arc (start 1.27 0) (end -1.29 -1.54483) (angle 148.9) (layer F.SilkS) (width 0.12))
(fp_arc (start 1.27 0) (end -1.23 -1.469694) (angle 299.1) (layer F.Fab) (width 0.1))
(pad 2 thru_hole circle (at 2.54 0 90) (size 1.8 1.8) (drill 0.9) (layers *.Cu *.Mask)
(net 23 V_LED))
(pad 1 thru_hole rect (at 0 0 90) (size 1.8 1.8) (drill 0.9) (layers *.Cu *.Mask)
(net 34 "Net-(D116-Pad1)"))
(model ${KISYS3DMOD}/LED_THT.3dshapes/LED_D5.0mm.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
Schematic: Bugfixes, VU meter draft, first development PCB draft
2020-11-02 00:00:47 +00:00
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
)
(module LED_THT:LED_D5.0mm locked (layer F.Cu) (tedit 5995936A) (tstamp 60B1C452)
(at 83 69.54 90)
(descr "LED, diameter 5.0mm, 2 pins, http://cdn-reichelt.de/documents/datenblatt/A500/LL-504BC2E-009.pdf")
(tags "LED diameter 5.0mm 2 pins")
(path /60B4284D)
(fp_text reference D115 (at 1.27 -3.96 90) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value ye (at 1.27 3.96 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_circle (center 1.27 0) (end 3.77 0) (layer F.Fab) (width 0.1))
(fp_circle (center 1.27 0) (end 3.77 0) (layer F.SilkS) (width 0.12))
(fp_line (start -1.23 -1.469694) (end -1.23 1.469694) (layer F.Fab) (width 0.1))
(fp_line (start -1.29 -1.545) (end -1.29 1.545) (layer F.SilkS) (width 0.12))
(fp_line (start -1.95 -3.25) (end -1.95 3.25) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.95 3.25) (end 4.5 3.25) (layer F.CrtYd) (width 0.05))
(fp_line (start 4.5 3.25) (end 4.5 -3.25) (layer F.CrtYd) (width 0.05))
(fp_line (start 4.5 -3.25) (end -1.95 -3.25) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 1.25 0 90) (layer F.Fab)
(effects (font (size 0.8 0.8) (thickness 0.2)))
)
(fp_arc (start 1.27 0) (end -1.29 1.54483) (angle -148.9) (layer F.SilkS) (width 0.12))
(fp_arc (start 1.27 0) (end -1.29 -1.54483) (angle 148.9) (layer F.SilkS) (width 0.12))
(fp_arc (start 1.27 0) (end -1.23 -1.469694) (angle 299.1) (layer F.Fab) (width 0.1))
(pad 2 thru_hole circle (at 2.54 0 90) (size 1.8 1.8) (drill 0.9) (layers *.Cu *.Mask)
(net 23 V_LED))
(pad 1 thru_hole rect (at 0 0 90) (size 1.8 1.8) (drill 0.9) (layers *.Cu *.Mask)
(net 33 "Net-(D115-Pad1)"))
(model ${KISYS3DMOD}/LED_THT.3dshapes/LED_D5.0mm.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
Schematic: Bugfixes, VU meter draft, first development PCB draft
2020-11-02 00:00:47 +00:00
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
)
(module LED_THT:LED_D5.0mm locked (layer F.Cu) (tedit 5995936A) (tstamp 60B1C440)
(at 83 76.04 90)
(descr "LED, diameter 5.0mm, 2 pins, http://cdn-reichelt.de/documents/datenblatt/A500/LL-504BC2E-009.pdf")
(tags "LED diameter 5.0mm 2 pins")
(path /60B4285E)
(fp_text reference D114 (at 1.27 -3.96 90) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value gn (at 1.27 3.96 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_circle (center 1.27 0) (end 3.77 0) (layer F.Fab) (width 0.1))
(fp_circle (center 1.27 0) (end 3.77 0) (layer F.SilkS) (width 0.12))
(fp_line (start -1.23 -1.469694) (end -1.23 1.469694) (layer F.Fab) (width 0.1))
(fp_line (start -1.29 -1.545) (end -1.29 1.545) (layer F.SilkS) (width 0.12))
(fp_line (start -1.95 -3.25) (end -1.95 3.25) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.95 3.25) (end 4.5 3.25) (layer F.CrtYd) (width 0.05))
(fp_line (start 4.5 3.25) (end 4.5 -3.25) (layer F.CrtYd) (width 0.05))
(fp_line (start 4.5 -3.25) (end -1.95 -3.25) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 1.25 0 90) (layer F.Fab)
(effects (font (size 0.8 0.8) (thickness 0.2)))
)
(fp_arc (start 1.27 0) (end -1.29 1.54483) (angle -148.9) (layer F.SilkS) (width 0.12))
(fp_arc (start 1.27 0) (end -1.29 -1.54483) (angle 148.9) (layer F.SilkS) (width 0.12))
(fp_arc (start 1.27 0) (end -1.23 -1.469694) (angle 299.1) (layer F.Fab) (width 0.1))
(pad 2 thru_hole circle (at 2.54 0 90) (size 1.8 1.8) (drill 0.9) (layers *.Cu *.Mask)
(net 23 V_LED))
(pad 1 thru_hole rect (at 0 0 90) (size 1.8 1.8) (drill 0.9) (layers *.Cu *.Mask)
(net 32 "Net-(D114-Pad1)"))
(model ${KISYS3DMOD}/LED_THT.3dshapes/LED_D5.0mm.wrl
Schematic: Bugfixes, VU meter draft, first development PCB draft
2020-11-02 00:00:47 +00:00
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(module LED_THT:LED_D5.0mm locked (layer F.Cu) (tedit 5995936A) (tstamp 60B1C42E)
(at 83 82.54 90)
(descr "LED, diameter 5.0mm, 2 pins, http://cdn-reichelt.de/documents/datenblatt/A500/LL-504BC2E-009.pdf")
(tags "LED diameter 5.0mm 2 pins")
(path /60B4286F)
(fp_text reference D113 (at 1.27 -3.96 90) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value gn (at 1.27 3.96 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_circle (center 1.27 0) (end 3.77 0) (layer F.Fab) (width 0.1))
(fp_circle (center 1.27 0) (end 3.77 0) (layer F.SilkS) (width 0.12))
(fp_line (start -1.23 -1.469694) (end -1.23 1.469694) (layer F.Fab) (width 0.1))
(fp_line (start -1.29 -1.545) (end -1.29 1.545) (layer F.SilkS) (width 0.12))
(fp_line (start -1.95 -3.25) (end -1.95 3.25) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.95 3.25) (end 4.5 3.25) (layer F.CrtYd) (width 0.05))
(fp_line (start 4.5 3.25) (end 4.5 -3.25) (layer F.CrtYd) (width 0.05))
(fp_line (start 4.5 -3.25) (end -1.95 -3.25) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 1.25 0 90) (layer F.Fab)
(effects (font (size 0.8 0.8) (thickness 0.2)))
)
(fp_arc (start 1.27 0) (end -1.29 1.54483) (angle -148.9) (layer F.SilkS) (width 0.12))
(fp_arc (start 1.27 0) (end -1.29 -1.54483) (angle 148.9) (layer F.SilkS) (width 0.12))
(fp_arc (start 1.27 0) (end -1.23 -1.469694) (angle 299.1) (layer F.Fab) (width 0.1))
(pad 2 thru_hole circle (at 2.54 0 90) (size 1.8 1.8) (drill 0.9) (layers *.Cu *.Mask)
(net 23 V_LED))
(pad 1 thru_hole rect (at 0 0 90) (size 1.8 1.8) (drill 0.9) (layers *.Cu *.Mask)
(net 31 "Net-(D113-Pad1)"))
(model ${KISYS3DMOD}/LED_THT.3dshapes/LED_D5.0mm.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
Schematic: Bugfixes, VU meter draft, first development PCB draft
2020-11-02 00:00:47 +00:00
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
)
(module LED_THT:LED_D5.0mm locked (layer F.Cu) (tedit 5995936A) (tstamp 60B1C41C)
(at 83 89.04 90)
(descr "LED, diameter 5.0mm, 2 pins, http://cdn-reichelt.de/documents/datenblatt/A500/LL-504BC2E-009.pdf")
(tags "LED diameter 5.0mm 2 pins")
(path /60B42880)
(fp_text reference D112 (at 1.27 -3.96 90) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value gn (at 1.27 3.96 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_circle (center 1.27 0) (end 3.77 0) (layer F.Fab) (width 0.1))
(fp_circle (center 1.27 0) (end 3.77 0) (layer F.SilkS) (width 0.12))
(fp_line (start -1.23 -1.469694) (end -1.23 1.469694) (layer F.Fab) (width 0.1))
(fp_line (start -1.29 -1.545) (end -1.29 1.545) (layer F.SilkS) (width 0.12))
(fp_line (start -1.95 -3.25) (end -1.95 3.25) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.95 3.25) (end 4.5 3.25) (layer F.CrtYd) (width 0.05))
(fp_line (start 4.5 3.25) (end 4.5 -3.25) (layer F.CrtYd) (width 0.05))
(fp_line (start 4.5 -3.25) (end -1.95 -3.25) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 1.25 0 90) (layer F.Fab)
(effects (font (size 0.8 0.8) (thickness 0.2)))
)
(fp_arc (start 1.27 0) (end -1.29 1.54483) (angle -148.9) (layer F.SilkS) (width 0.12))
(fp_arc (start 1.27 0) (end -1.29 -1.54483) (angle 148.9) (layer F.SilkS) (width 0.12))
(fp_arc (start 1.27 0) (end -1.23 -1.469694) (angle 299.1) (layer F.Fab) (width 0.1))
(pad 2 thru_hole circle (at 2.54 0 90) (size 1.8 1.8) (drill 0.9) (layers *.Cu *.Mask)
(net 23 V_LED))
(pad 1 thru_hole rect (at 0 0 90) (size 1.8 1.8) (drill 0.9) (layers *.Cu *.Mask)
(net 30 "Net-(D112-Pad1)"))
(model ${KISYS3DMOD}/LED_THT.3dshapes/LED_D5.0mm.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
Schematic: Bugfixes, VU meter draft, first development PCB draft
2020-11-02 00:00:47 +00:00
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
)
(module LED_THT:LED_D5.0mm locked (layer F.Cu) (tedit 5995936A) (tstamp 60B1C40A)
(at 83 95.54 90)
(descr "LED, diameter 5.0mm, 2 pins, http://cdn-reichelt.de/documents/datenblatt/A500/LL-504BC2E-009.pdf")
(tags "LED diameter 5.0mm 2 pins")
(path /60B42891)
(fp_text reference D111 (at 1.27 -3.96 90) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value ye (at 1.27 3.96 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_circle (center 1.27 0) (end 3.77 0) (layer F.Fab) (width 0.1))
(fp_circle (center 1.27 0) (end 3.77 0) (layer F.SilkS) (width 0.12))
(fp_line (start -1.23 -1.469694) (end -1.23 1.469694) (layer F.Fab) (width 0.1))
(fp_line (start -1.29 -1.545) (end -1.29 1.545) (layer F.SilkS) (width 0.12))
(fp_line (start -1.95 -3.25) (end -1.95 3.25) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.95 3.25) (end 4.5 3.25) (layer F.CrtYd) (width 0.05))
(fp_line (start 4.5 3.25) (end 4.5 -3.25) (layer F.CrtYd) (width 0.05))
(fp_line (start 4.5 -3.25) (end -1.95 -3.25) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 1.25 0 90) (layer F.Fab)
(effects (font (size 0.8 0.8) (thickness 0.2)))
)
(fp_arc (start 1.27 0) (end -1.29 1.54483) (angle -148.9) (layer F.SilkS) (width 0.12))
(fp_arc (start 1.27 0) (end -1.29 -1.54483) (angle 148.9) (layer F.SilkS) (width 0.12))
(fp_arc (start 1.27 0) (end -1.23 -1.469694) (angle 299.1) (layer F.Fab) (width 0.1))
(pad 2 thru_hole circle (at 2.54 0 90) (size 1.8 1.8) (drill 0.9) (layers *.Cu *.Mask)
(net 23 V_LED))
(pad 1 thru_hole rect (at 0 0 90) (size 1.8 1.8) (drill 0.9) (layers *.Cu *.Mask)
(net 29 "Net-(D111-Pad1)"))
(model ${KISYS3DMOD}/LED_THT.3dshapes/LED_D5.0mm.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
)
(module LED_THT:LED_D5.0mm locked (layer F.Cu) (tedit 5995936A) (tstamp 60B1C3F8)
(at 83 102.04 90)
(descr "LED, diameter 5.0mm, 2 pins, http://cdn-reichelt.de/documents/datenblatt/A500/LL-504BC2E-009.pdf")
(tags "LED diameter 5.0mm 2 pins")
(path /60B428A2)
(fp_text reference D110 (at 1.27 -3.96 90) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value ye (at 1.27 3.96 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_circle (center 1.27 0) (end 3.77 0) (layer F.Fab) (width 0.1))
(fp_circle (center 1.27 0) (end 3.77 0) (layer F.SilkS) (width 0.12))
(fp_line (start -1.23 -1.469694) (end -1.23 1.469694) (layer F.Fab) (width 0.1))
(fp_line (start -1.29 -1.545) (end -1.29 1.545) (layer F.SilkS) (width 0.12))
(fp_line (start -1.95 -3.25) (end -1.95 3.25) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.95 3.25) (end 4.5 3.25) (layer F.CrtYd) (width 0.05))
(fp_line (start 4.5 3.25) (end 4.5 -3.25) (layer F.CrtYd) (width 0.05))
(fp_line (start 4.5 -3.25) (end -1.95 -3.25) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 1.25 0 90) (layer F.Fab)
(effects (font (size 0.8 0.8) (thickness 0.2)))
)
(fp_arc (start 1.27 0) (end -1.29 1.54483) (angle -148.9) (layer F.SilkS) (width 0.12))
(fp_arc (start 1.27 0) (end -1.29 -1.54483) (angle 148.9) (layer F.SilkS) (width 0.12))
(fp_arc (start 1.27 0) (end -1.23 -1.469694) (angle 299.1) (layer F.Fab) (width 0.1))
(pad 2 thru_hole circle (at 2.54 0 90) (size 1.8 1.8) (drill 0.9) (layers *.Cu *.Mask)
(net 23 V_LED))
(pad 1 thru_hole rect (at 0 0 90) (size 1.8 1.8) (drill 0.9) (layers *.Cu *.Mask)
(net 28 "Net-(D110-Pad1)"))
(model ${KISYS3DMOD}/LED_THT.3dshapes/LED_D5.0mm.wrl
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(module LED_THT:LED_D5.0mm locked (layer F.Cu) (tedit 5995936A) (tstamp 60B1C3E6)
(at 83 108.54 90)
(descr "LED, diameter 5.0mm, 2 pins, http://cdn-reichelt.de/documents/datenblatt/A500/LL-504BC2E-009.pdf")
(tags "LED diameter 5.0mm 2 pins")
(path /60B428B3)
(fp_text reference D109 (at 1.27 -3.96 90) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value rd (at 1.27 3.96 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_circle (center 1.27 0) (end 3.77 0) (layer F.Fab) (width 0.1))
(fp_circle (center 1.27 0) (end 3.77 0) (layer F.SilkS) (width 0.12))
(fp_line (start -1.23 -1.469694) (end -1.23 1.469694) (layer F.Fab) (width 0.1))
(fp_line (start -1.29 -1.545) (end -1.29 1.545) (layer F.SilkS) (width 0.12))
(fp_line (start -1.95 -3.25) (end -1.95 3.25) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.95 3.25) (end 4.5 3.25) (layer F.CrtYd) (width 0.05))
(fp_line (start 4.5 3.25) (end 4.5 -3.25) (layer F.CrtYd) (width 0.05))
(fp_line (start 4.5 -3.25) (end -1.95 -3.25) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 1.25 0 90) (layer F.Fab)
(effects (font (size 0.8 0.8) (thickness 0.2)))
)
(fp_arc (start 1.27 0) (end -1.29 1.54483) (angle -148.9) (layer F.SilkS) (width 0.12))
(fp_arc (start 1.27 0) (end -1.29 -1.54483) (angle 148.9) (layer F.SilkS) (width 0.12))
(fp_arc (start 1.27 0) (end -1.23 -1.469694) (angle 299.1) (layer F.Fab) (width 0.1))
(pad 2 thru_hole circle (at 2.54 0 90) (size 1.8 1.8) (drill 0.9) (layers *.Cu *.Mask)
(net 23 V_LED))
(pad 1 thru_hole rect (at 0 0 90) (size 1.8 1.8) (drill 0.9) (layers *.Cu *.Mask)
(net 27 "Net-(D109-Pad1)"))
(model ${KISYS3DMOD}/LED_THT.3dshapes/LED_D5.0mm.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
)
(module LED_THT:LED_D5.0mm locked (layer F.Cu) (tedit 5995936A) (tstamp 60B1C3D4)
(at 83 115.04 90)
(descr "LED, diameter 5.0mm, 2 pins, http://cdn-reichelt.de/documents/datenblatt/A500/LL-504BC2E-009.pdf")
(tags "LED diameter 5.0mm 2 pins")
(path /60B428C4)
(fp_text reference D108 (at 1.27 -3.96 90) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value rd (at 1.27 3.96 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_circle (center 1.27 0) (end 3.77 0) (layer F.Fab) (width 0.1))
(fp_circle (center 1.27 0) (end 3.77 0) (layer F.SilkS) (width 0.12))
(fp_line (start -1.23 -1.469694) (end -1.23 1.469694) (layer F.Fab) (width 0.1))
(fp_line (start -1.29 -1.545) (end -1.29 1.545) (layer F.SilkS) (width 0.12))
(fp_line (start -1.95 -3.25) (end -1.95 3.25) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.95 3.25) (end 4.5 3.25) (layer F.CrtYd) (width 0.05))
(fp_line (start 4.5 3.25) (end 4.5 -3.25) (layer F.CrtYd) (width 0.05))
(fp_line (start 4.5 -3.25) (end -1.95 -3.25) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 1.25 0 90) (layer F.Fab)
(effects (font (size 0.8 0.8) (thickness 0.2)))
)
(fp_arc (start 1.27 0) (end -1.29 1.54483) (angle -148.9) (layer F.SilkS) (width 0.12))
(fp_arc (start 1.27 0) (end -1.29 -1.54483) (angle 148.9) (layer F.SilkS) (width 0.12))
(fp_arc (start 1.27 0) (end -1.23 -1.469694) (angle 299.1) (layer F.Fab) (width 0.1))
(pad 2 thru_hole circle (at 2.54 0 90) (size 1.8 1.8) (drill 0.9) (layers *.Cu *.Mask)
(net 23 V_LED))
(pad 1 thru_hole rect (at 0 0 90) (size 1.8 1.8) (drill 0.9) (layers *.Cu *.Mask)
(net 26 "Net-(D108-Pad1)"))
(model ${KISYS3DMOD}/LED_THT.3dshapes/LED_D5.0mm.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
)
(module LED_THT:LED_D5.0mm locked (layer F.Cu) (tedit 5995936A) (tstamp 60B1C3C2)
(at 83 121.54 90)
(descr "LED, diameter 5.0mm, 2 pins, http://cdn-reichelt.de/documents/datenblatt/A500/LL-504BC2E-009.pdf")
(tags "LED diameter 5.0mm 2 pins")
(path /60B428D5)
(fp_text reference D107 (at 1.27 -3.96 90) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value rd (at 1.27 3.96 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_circle (center 1.27 0) (end 3.77 0) (layer F.Fab) (width 0.1))
(fp_circle (center 1.27 0) (end 3.77 0) (layer F.SilkS) (width 0.12))
(fp_line (start -1.23 -1.469694) (end -1.23 1.469694) (layer F.Fab) (width 0.1))
(fp_line (start -1.29 -1.545) (end -1.29 1.545) (layer F.SilkS) (width 0.12))
(fp_line (start -1.95 -3.25) (end -1.95 3.25) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.95 3.25) (end 4.5 3.25) (layer F.CrtYd) (width 0.05))
(fp_line (start 4.5 3.25) (end 4.5 -3.25) (layer F.CrtYd) (width 0.05))
(fp_line (start 4.5 -3.25) (end -1.95 -3.25) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 1.25 0 90) (layer F.Fab)
(effects (font (size 0.8 0.8) (thickness 0.2)))
)
(fp_arc (start 1.27 0) (end -1.29 1.54483) (angle -148.9) (layer F.SilkS) (width 0.12))
(fp_arc (start 1.27 0) (end -1.29 -1.54483) (angle 148.9) (layer F.SilkS) (width 0.12))
(fp_arc (start 1.27 0) (end -1.23 -1.469694) (angle 299.1) (layer F.Fab) (width 0.1))
(pad 2 thru_hole circle (at 2.54 0 90) (size 1.8 1.8) (drill 0.9) (layers *.Cu *.Mask)
(net 23 V_LED))
(pad 1 thru_hole rect (at 0 0 90) (size 1.8 1.8) (drill 0.9) (layers *.Cu *.Mask)
(net 25 "Net-(D107-Pad1)"))
(model ${KISYS3DMOD}/LED_THT.3dshapes/LED_D5.0mm.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
)
(module LED_THT:LED_D5.0mm locked (layer F.Cu) (tedit 5995936A) (tstamp 60B1C3B0)
(at 83 128.04 90)
(descr "LED, diameter 5.0mm, 2 pins, http://cdn-reichelt.de/documents/datenblatt/A500/LL-504BC2E-009.pdf")
(tags "LED diameter 5.0mm 2 pins")
(path /60B428E6)
(fp_text reference D106 (at 1.27 -3.96 90) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value rd (at 1.27 3.96 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_circle (center 1.27 0) (end 3.77 0) (layer F.Fab) (width 0.1))
(fp_circle (center 1.27 0) (end 3.77 0) (layer F.SilkS) (width 0.12))
(fp_line (start -1.23 -1.469694) (end -1.23 1.469694) (layer F.Fab) (width 0.1))
(fp_line (start -1.29 -1.545) (end -1.29 1.545) (layer F.SilkS) (width 0.12))
(fp_line (start -1.95 -3.25) (end -1.95 3.25) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.95 3.25) (end 4.5 3.25) (layer F.CrtYd) (width 0.05))
(fp_line (start 4.5 3.25) (end 4.5 -3.25) (layer F.CrtYd) (width 0.05))
(fp_line (start 4.5 -3.25) (end -1.95 -3.25) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 1.25 0 90) (layer F.Fab)
(effects (font (size 0.8 0.8) (thickness 0.2)))
)
(fp_arc (start 1.27 0) (end -1.29 1.54483) (angle -148.9) (layer F.SilkS) (width 0.12))
(fp_arc (start 1.27 0) (end -1.29 -1.54483) (angle 148.9) (layer F.SilkS) (width 0.12))
(fp_arc (start 1.27 0) (end -1.23 -1.469694) (angle 299.1) (layer F.Fab) (width 0.1))
(pad 2 thru_hole circle (at 2.54 0 90) (size 1.8 1.8) (drill 0.9) (layers *.Cu *.Mask)
(net 23 V_LED))
(pad 1 thru_hole rect (at 0 0 90) (size 1.8 1.8) (drill 0.9) (layers *.Cu *.Mask)
(net 24 "Net-(D106-Pad1)"))
(model ${KISYS3DMOD}/LED_THT.3dshapes/LED_D5.0mm.wrl
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(module LED_THT:LED_D5.0mm locked (layer F.Cu) (tedit 5995936A) (tstamp 60B1C326)
(at 57 68.5 270)
(descr "LED, diameter 5.0mm, 2 pins, http://cdn-reichelt.de/documents/datenblatt/A500/LL-504BC2E-009.pdf")
(tags "LED diameter 5.0mm 2 pins")
(path /60DE68F1)
(fp_text reference D101 (at 1.27 -3.96 90) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value "On-Air (rd)" (at 1.27 3.96 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_circle (center 1.27 0) (end 3.77 0) (layer F.Fab) (width 0.1))
(fp_circle (center 1.27 0) (end 3.77 0) (layer F.SilkS) (width 0.12))
(fp_line (start -1.23 -1.469694) (end -1.23 1.469694) (layer F.Fab) (width 0.1))
(fp_line (start -1.29 -1.545) (end -1.29 1.545) (layer F.SilkS) (width 0.12))
(fp_line (start -1.95 -3.25) (end -1.95 3.25) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.95 3.25) (end 4.5 3.25) (layer F.CrtYd) (width 0.05))
(fp_line (start 4.5 3.25) (end 4.5 -3.25) (layer F.CrtYd) (width 0.05))
(fp_line (start 4.5 -3.25) (end -1.95 -3.25) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 1.25 0 90) (layer F.Fab)
(effects (font (size 0.8 0.8) (thickness 0.2)))
)
(fp_arc (start 1.27 0) (end -1.29 1.54483) (angle -148.9) (layer F.SilkS) (width 0.12))
(fp_arc (start 1.27 0) (end -1.29 -1.54483) (angle 148.9) (layer F.SilkS) (width 0.12))
(fp_arc (start 1.27 0) (end -1.23 -1.469694) (angle 299.1) (layer F.Fab) (width 0.1))
(pad 2 thru_hole circle (at 2.54 0 270) (size 1.8 1.8) (drill 0.9) (layers *.Cu *.Mask)
(net 21 "Net-(D101-Pad2)"))
(pad 1 thru_hole rect (at 0 0 270) (size 1.8 1.8) (drill 0.9) (layers *.Cu *.Mask)
(net 22 "Net-(D101-Pad1)"))
(model ${KISYS3DMOD}/LED_THT.3dshapes/LED_D5.0mm.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
)
(module Capacitor_THT:C_Disc_D5.0mm_W2.5mm_P5.00mm (layer B.Cu) (tedit 5AE50EF0) (tstamp 60B1C314)
(at 102.87 76.2)
(descr "C, Disc series, Radial, pin pitch=5.00mm, , diameter*width=5*2.5mm^2, Capacitor, http://cdn-reichelt.de/documents/datenblatt/B300/DS_KERKO_TC.pdf")
(tags "C Disc series Radial pin pitch 5.00mm diameter 5mm width 2.5mm Capacitor")
(path /60B429F3)
(fp_text reference C125 (at 2.5 2.5) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value 100nF (at 2.5 -2.5) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_line (start 0 1.25) (end 0 -1.25) (layer B.Fab) (width 0.1))
(fp_line (start 0 -1.25) (end 5 -1.25) (layer B.Fab) (width 0.1))
(fp_line (start 5 -1.25) (end 5 1.25) (layer B.Fab) (width 0.1))
(fp_line (start 5 1.25) (end 0 1.25) (layer B.Fab) (width 0.1))
(fp_line (start -0.12 1.37) (end 5.12 1.37) (layer B.SilkS) (width 0.12))
(fp_line (start -0.12 -1.37) (end 5.12 -1.37) (layer B.SilkS) (width 0.12))
(fp_line (start -0.12 1.37) (end -0.12 1.055) (layer B.SilkS) (width 0.12))
(fp_line (start -0.12 -1.055) (end -0.12 -1.37) (layer B.SilkS) (width 0.12))
(fp_line (start 5.12 1.37) (end 5.12 1.055) (layer B.SilkS) (width 0.12))
(fp_line (start 5.12 -1.055) (end 5.12 -1.37) (layer B.SilkS) (width 0.12))
(fp_line (start -1.05 1.5) (end -1.05 -1.5) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.05 -1.5) (end 6.05 -1.5) (layer B.CrtYd) (width 0.05))
(fp_line (start 6.05 -1.5) (end 6.05 1.5) (layer B.CrtYd) (width 0.05))
(fp_line (start 6.05 1.5) (end -1.05 1.5) (layer B.CrtYd) (width 0.05))
(fp_text user %R (at 2.5 0) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(pad 2 thru_hole circle (at 5 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 3 GND))
(pad 1 thru_hole circle (at 0 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 2 +15V))
(model ${KISYS3DMOD}/Capacitor_THT.3dshapes/C_Disc_D5.0mm_W2.5mm_P5.00mm.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
)
(module Capacitor_THT:C_Disc_D5.0mm_W2.5mm_P5.00mm (layer B.Cu) (tedit 5AE50EF0) (tstamp 60B1C2FF)
(at 102.87 101.6)
(descr "C, Disc series, Radial, pin pitch=5.00mm, , diameter*width=5*2.5mm^2, Capacitor, http://cdn-reichelt.de/documents/datenblatt/B300/DS_KERKO_TC.pdf")
(tags "C Disc series Radial pin pitch 5.00mm diameter 5mm width 2.5mm Capacitor")
(path /60B429CA)
(fp_text reference C124 (at 2.5 2.5) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value 100nF (at 2.5 -2.5) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_line (start 0 1.25) (end 0 -1.25) (layer B.Fab) (width 0.1))
(fp_line (start 0 -1.25) (end 5 -1.25) (layer B.Fab) (width 0.1))
(fp_line (start 5 -1.25) (end 5 1.25) (layer B.Fab) (width 0.1))
(fp_line (start 5 1.25) (end 0 1.25) (layer B.Fab) (width 0.1))
(fp_line (start -0.12 1.37) (end 5.12 1.37) (layer B.SilkS) (width 0.12))
(fp_line (start -0.12 -1.37) (end 5.12 -1.37) (layer B.SilkS) (width 0.12))
(fp_line (start -0.12 1.37) (end -0.12 1.055) (layer B.SilkS) (width 0.12))
(fp_line (start -0.12 -1.055) (end -0.12 -1.37) (layer B.SilkS) (width 0.12))
(fp_line (start 5.12 1.37) (end 5.12 1.055) (layer B.SilkS) (width 0.12))
(fp_line (start 5.12 -1.055) (end 5.12 -1.37) (layer B.SilkS) (width 0.12))
(fp_line (start -1.05 1.5) (end -1.05 -1.5) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.05 -1.5) (end 6.05 -1.5) (layer B.CrtYd) (width 0.05))
(fp_line (start 6.05 -1.5) (end 6.05 1.5) (layer B.CrtYd) (width 0.05))
(fp_line (start 6.05 1.5) (end -1.05 1.5) (layer B.CrtYd) (width 0.05))
(fp_text user %R (at 2.5 0) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(pad 2 thru_hole circle (at 5 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 3 GND))
(pad 1 thru_hole circle (at 0 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 2 +15V))
(model ${KISYS3DMOD}/Capacitor_THT.3dshapes/C_Disc_D5.0mm_W2.5mm_P5.00mm.wrl
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(module Capacitor_THT:C_Disc_D5.0mm_W2.5mm_P5.00mm (layer B.Cu) (tedit 5AE50EF0) (tstamp 60B1C2EA)
(at 102.87 127)
(descr "C, Disc series, Radial, pin pitch=5.00mm, , diameter*width=5*2.5mm^2, Capacitor, http://cdn-reichelt.de/documents/datenblatt/B300/DS_KERKO_TC.pdf")
(tags "C Disc series Radial pin pitch 5.00mm diameter 5mm width 2.5mm Capacitor")
(path /60B42998)
(fp_text reference C123 (at 2.5 2.5) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value 100nF (at 2.5 -2.5) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_line (start 0 1.25) (end 0 -1.25) (layer B.Fab) (width 0.1))
(fp_line (start 0 -1.25) (end 5 -1.25) (layer B.Fab) (width 0.1))
(fp_line (start 5 -1.25) (end 5 1.25) (layer B.Fab) (width 0.1))
(fp_line (start 5 1.25) (end 0 1.25) (layer B.Fab) (width 0.1))
(fp_line (start -0.12 1.37) (end 5.12 1.37) (layer B.SilkS) (width 0.12))
(fp_line (start -0.12 -1.37) (end 5.12 -1.37) (layer B.SilkS) (width 0.12))
(fp_line (start -0.12 1.37) (end -0.12 1.055) (layer B.SilkS) (width 0.12))
(fp_line (start -0.12 -1.055) (end -0.12 -1.37) (layer B.SilkS) (width 0.12))
(fp_line (start 5.12 1.37) (end 5.12 1.055) (layer B.SilkS) (width 0.12))
(fp_line (start 5.12 -1.055) (end 5.12 -1.37) (layer B.SilkS) (width 0.12))
(fp_line (start -1.05 1.5) (end -1.05 -1.5) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.05 -1.5) (end 6.05 -1.5) (layer B.CrtYd) (width 0.05))
(fp_line (start 6.05 -1.5) (end 6.05 1.5) (layer B.CrtYd) (width 0.05))
(fp_line (start 6.05 1.5) (end -1.05 1.5) (layer B.CrtYd) (width 0.05))
(fp_text user %R (at 2.5 0) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(pad 2 thru_hole circle (at 5 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 3 GND))
(pad 1 thru_hole circle (at 0 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 2 +15V))
(model ${KISYS3DMOD}/Capacitor_THT.3dshapes/C_Disc_D5.0mm_W2.5mm_P5.00mm.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Capacitor_THT:C_Disc_D5.0mm_W2.5mm_P5.00mm (layer B.Cu) (tedit 5AE50EF0) (tstamp 60B1C2D5)
(at 121.92 135.89 180)
(descr "C, Disc series, Radial, pin pitch=5.00mm, , diameter*width=5*2.5mm^2, Capacitor, http://cdn-reichelt.de/documents/datenblatt/B300/DS_KERKO_TC.pdf")
(tags "C Disc series Radial pin pitch 5.00mm diameter 5mm width 2.5mm Capacitor")
(path /60B4293A)
(fp_text reference C122 (at 2.5 2.5) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value 100nF (at 2.5 -2.5) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_line (start 0 1.25) (end 0 -1.25) (layer B.Fab) (width 0.1))
(fp_line (start 0 -1.25) (end 5 -1.25) (layer B.Fab) (width 0.1))
(fp_line (start 5 -1.25) (end 5 1.25) (layer B.Fab) (width 0.1))
(fp_line (start 5 1.25) (end 0 1.25) (layer B.Fab) (width 0.1))
(fp_line (start -0.12 1.37) (end 5.12 1.37) (layer B.SilkS) (width 0.12))
(fp_line (start -0.12 -1.37) (end 5.12 -1.37) (layer B.SilkS) (width 0.12))
(fp_line (start -0.12 1.37) (end -0.12 1.055) (layer B.SilkS) (width 0.12))
(fp_line (start -0.12 -1.055) (end -0.12 -1.37) (layer B.SilkS) (width 0.12))
(fp_line (start 5.12 1.37) (end 5.12 1.055) (layer B.SilkS) (width 0.12))
(fp_line (start 5.12 -1.055) (end 5.12 -1.37) (layer B.SilkS) (width 0.12))
(fp_line (start -1.05 1.5) (end -1.05 -1.5) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.05 -1.5) (end 6.05 -1.5) (layer B.CrtYd) (width 0.05))
(fp_line (start 6.05 -1.5) (end 6.05 1.5) (layer B.CrtYd) (width 0.05))
(fp_line (start 6.05 1.5) (end -1.05 1.5) (layer B.CrtYd) (width 0.05))
(fp_text user %R (at 2.5 0) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(pad 2 thru_hole circle (at 5 0 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 2 +15V))
(pad 1 thru_hole circle (at 0 0 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 3 GND))
(model ${KISYS3DMOD}/Capacitor_THT.3dshapes/C_Disc_D5.0mm_W2.5mm_P5.00mm.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Capacitor_THT:C_Disc_D5.0mm_W2.5mm_P5.00mm (layer B.Cu) (tedit 5AE50EF0) (tstamp 60B1C2C0)
(at 116.92 153.67)
(descr "C, Disc series, Radial, pin pitch=5.00mm, , diameter*width=5*2.5mm^2, Capacitor, http://cdn-reichelt.de/documents/datenblatt/B300/DS_KERKO_TC.pdf")
(tags "C Disc series Radial pin pitch 5.00mm diameter 5mm width 2.5mm Capacitor")
(path /60B42A28)
(fp_text reference C121 (at 2.5 2.5) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value 100nF (at 2.5 -2.5) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_line (start 0 1.25) (end 0 -1.25) (layer B.Fab) (width 0.1))
(fp_line (start 0 -1.25) (end 5 -1.25) (layer B.Fab) (width 0.1))
(fp_line (start 5 -1.25) (end 5 1.25) (layer B.Fab) (width 0.1))
(fp_line (start 5 1.25) (end 0 1.25) (layer B.Fab) (width 0.1))
(fp_line (start -0.12 1.37) (end 5.12 1.37) (layer B.SilkS) (width 0.12))
(fp_line (start -0.12 -1.37) (end 5.12 -1.37) (layer B.SilkS) (width 0.12))
(fp_line (start -0.12 1.37) (end -0.12 1.055) (layer B.SilkS) (width 0.12))
(fp_line (start -0.12 -1.055) (end -0.12 -1.37) (layer B.SilkS) (width 0.12))
(fp_line (start 5.12 1.37) (end 5.12 1.055) (layer B.SilkS) (width 0.12))
(fp_line (start 5.12 -1.055) (end 5.12 -1.37) (layer B.SilkS) (width 0.12))
(fp_line (start -1.05 1.5) (end -1.05 -1.5) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.05 -1.5) (end 6.05 -1.5) (layer B.CrtYd) (width 0.05))
(fp_line (start 6.05 -1.5) (end 6.05 1.5) (layer B.CrtYd) (width 0.05))
(fp_line (start 6.05 1.5) (end -1.05 1.5) (layer B.CrtYd) (width 0.05))
(fp_text user %R (at 2.5 0) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(pad 2 thru_hole circle (at 5 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 1 -15V))
(pad 1 thru_hole circle (at 0 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 3 GND))
(model ${KISYS3DMOD}/Capacitor_THT.3dshapes/C_Disc_D5.0mm_W2.5mm_P5.00mm.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
)
(module Resistor_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal (layer F.Cu) (tedit 5AE5139B) (tstamp 5FD6DBC2)
(at 80.01 210.17 180)
(descr "Resistor, Axial_DIN0207 series, Axial, Horizontal, pin pitch=10.16mm, 0.25W = 1/4W, length*diameter=6.3*2.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf")
(tags "Resistor Axial_DIN0207 series Axial Horizontal pin pitch 10.16mm 0.25W = 1/4W length 6.3mm diameter 2.5mm")
(path /5FDA0F68)
(fp_text reference R111 (at 5.08 -2.37) (layer F.SilkS)
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(fp_text value "680R 1%" (at 5.08 2.37) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 1.93 -1.25) (end 1.93 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 1.93 1.25) (end 8.23 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 1.25) (end 8.23 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 -1.25) (end 1.93 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 0 0) (end 1.93 0) (layer F.Fab) (width 0.1))
(fp_line (start 10.16 0) (end 8.23 0) (layer F.Fab) (width 0.1))
(fp_line (start 1.81 -1.37) (end 1.81 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 1.81 1.37) (end 8.35 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 8.35 1.37) (end 8.35 -1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 8.35 -1.37) (end 1.81 -1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 1.04 0) (end 1.81 0) (layer F.SilkS) (width 0.12))
(fp_line (start 9.12 0) (end 8.35 0) (layer F.SilkS) (width 0.12))
(fp_line (start -1.05 -1.5) (end -1.05 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.5) (end 11.21 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 11.21 1.5) (end 11.21 -1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 11.21 -1.5) (end -1.05 -1.5) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 5.08 0) (layer F.Fab)
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(pad 2 thru_hole oval (at 10.16 0 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 12 V_Phant))
(pad 1 thru_hole circle (at 0 0 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 15 "Net-(C113-Pad1)"))
(model ${KISYS3DMOD}/Resistor_THT.3dshapes/R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal.wrl
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(module Resistor_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal (layer F.Cu) (tedit 5AE5139B) (tstamp 5FD6DAA3)
(at 62.23 210.17 180)
(descr "Resistor, Axial_DIN0207 series, Axial, Horizontal, pin pitch=10.16mm, 0.25W = 1/4W, length*diameter=6.3*2.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf")
(tags "Resistor Axial_DIN0207 series Axial Horizontal pin pitch 10.16mm 0.25W = 1/4W length 6.3mm diameter 2.5mm")
(path /5FD87CA8)
(fp_text reference R107 (at 5.08 -2.37) (layer F.SilkS)
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(fp_text value "680R 1%" (at 5.08 2.37) (layer F.Fab)
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(fp_line (start 1.93 -1.25) (end 1.93 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 1.93 1.25) (end 8.23 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 1.25) (end 8.23 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 -1.25) (end 1.93 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 0 0) (end 1.93 0) (layer F.Fab) (width 0.1))
(fp_line (start 10.16 0) (end 8.23 0) (layer F.Fab) (width 0.1))
(fp_line (start 1.81 -1.37) (end 1.81 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 1.81 1.37) (end 8.35 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 8.35 1.37) (end 8.35 -1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 8.35 -1.37) (end 1.81 -1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 1.04 0) (end 1.81 0) (layer F.SilkS) (width 0.12))
(fp_line (start 9.12 0) (end 8.35 0) (layer F.SilkS) (width 0.12))
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
(fp_line (start -1.05 -1.5) (end -1.05 1.5) (layer F.CrtYd) (width 0.05))
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(fp_line (start -1.05 1.5) (end 11.21 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 11.21 1.5) (end 11.21 -1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 11.21 -1.5) (end -1.05 -1.5) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 5.08 0) (layer F.Fab)
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(pad 2 thru_hole oval (at 10.16 0 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 7 "Net-(C107-Pad1)"))
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
(pad 1 thru_hole circle (at 0 0 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(net 12 V_Phant))
(model ${KISYS3DMOD}/Resistor_THT.3dshapes/R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal.wrl
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(module Diode_THT:D_DO-35_SOD27_P10.16mm_Horizontal (layer F.Cu) (tedit 5AE50CD5) (tstamp 5FD6D698)
(at 55.88 196.2 270)
(descr "Diode, DO-35_SOD27 series, Axial, Horizontal, pin pitch=10.16mm, , length*diameter=4*2mm^2, , http://www.diodes.com/_files/packages/DO-35.pdf")
(tags "Diode DO-35_SOD27 series Axial Horizontal pin pitch 10.16mm length 4mm diameter 2mm")
(path /60346518)
(fp_text reference D105 (at 5.08 -2.12 90) (layer F.SilkS)
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(fp_text value 1N4148 (at 5.08 2.12 90) (layer F.Fab)
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(fp_line (start 3.08 -1) (end 3.08 1) (layer F.Fab) (width 0.1))
(fp_line (start 3.08 1) (end 7.08 1) (layer F.Fab) (width 0.1))
(fp_line (start 7.08 1) (end 7.08 -1) (layer F.Fab) (width 0.1))
(fp_line (start 7.08 -1) (end 3.08 -1) (layer F.Fab) (width 0.1))
(fp_line (start 0 0) (end 3.08 0) (layer F.Fab) (width 0.1))
(fp_line (start 10.16 0) (end 7.08 0) (layer F.Fab) (width 0.1))
(fp_line (start 3.68 -1) (end 3.68 1) (layer F.Fab) (width 0.1))
(fp_line (start 3.78 -1) (end 3.78 1) (layer F.Fab) (width 0.1))
(fp_line (start 3.58 -1) (end 3.58 1) (layer F.Fab) (width 0.1))
(fp_line (start 2.96 -1.12) (end 2.96 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 2.96 1.12) (end 7.2 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 7.2 1.12) (end 7.2 -1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 7.2 -1.12) (end 2.96 -1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 1.04 0) (end 2.96 0) (layer F.SilkS) (width 0.12))
(fp_line (start 9.12 0) (end 7.2 0) (layer F.SilkS) (width 0.12))
(fp_line (start 3.68 -1.12) (end 3.68 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 3.8 -1.12) (end 3.8 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 3.56 -1.12) (end 3.56 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start -1.05 -1.25) (end -1.05 1.25) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.25) (end 11.21 1.25) (layer F.CrtYd) (width 0.05))
(fp_line (start 11.21 1.25) (end 11.21 -1.25) (layer F.CrtYd) (width 0.05))
(fp_line (start 11.21 -1.25) (end -1.05 -1.25) (layer F.CrtYd) (width 0.05))
(fp_text user K (at 0 -1.8 90) (layer F.SilkS)
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(fp_text user K (at 0 -1.8 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 5.38 0 90) (layer F.Fab)
(effects (font (size 0.8 0.8) (thickness 0.12)))
)
(pad 2 thru_hole oval (at 10.16 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 3 GND))
(pad 1 thru_hole rect (at 0 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 14 "Net-(C113-Pad2)"))
(model ${KISYS3DMOD}/Diode_THT.3dshapes/D_DO-35_SOD27_P10.16mm_Horizontal.wrl
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(module Diode_THT:D_DO-35_SOD27_P10.16mm_Horizontal (layer F.Cu) (tedit 5AE50CD5) (tstamp 5FD6D679)
(at 53.34 206.36 90)
(descr "Diode, DO-35_SOD27 series, Axial, Horizontal, pin pitch=10.16mm, , length*diameter=4*2mm^2, , http://www.diodes.com/_files/packages/DO-35.pdf")
(tags "Diode DO-35_SOD27 series Axial Horizontal pin pitch 10.16mm length 4mm diameter 2mm")
(path /6034651E)
(fp_text reference D104 (at 5.08 -2.12 90) (layer F.SilkS)
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(fp_text value 1N4148 (at 5.08 2.12 90) (layer F.Fab)
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(fp_line (start 3.08 -1) (end 3.08 1) (layer F.Fab) (width 0.1))
(fp_line (start 3.08 1) (end 7.08 1) (layer F.Fab) (width 0.1))
(fp_line (start 7.08 1) (end 7.08 -1) (layer F.Fab) (width 0.1))
(fp_line (start 7.08 -1) (end 3.08 -1) (layer F.Fab) (width 0.1))
(fp_line (start 0 0) (end 3.08 0) (layer F.Fab) (width 0.1))
(fp_line (start 10.16 0) (end 7.08 0) (layer F.Fab) (width 0.1))
(fp_line (start 3.68 -1) (end 3.68 1) (layer F.Fab) (width 0.1))
(fp_line (start 3.78 -1) (end 3.78 1) (layer F.Fab) (width 0.1))
(fp_line (start 3.58 -1) (end 3.58 1) (layer F.Fab) (width 0.1))
(fp_line (start 2.96 -1.12) (end 2.96 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 2.96 1.12) (end 7.2 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 7.2 1.12) (end 7.2 -1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 7.2 -1.12) (end 2.96 -1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 1.04 0) (end 2.96 0) (layer F.SilkS) (width 0.12))
(fp_line (start 9.12 0) (end 7.2 0) (layer F.SilkS) (width 0.12))
(fp_line (start 3.68 -1.12) (end 3.68 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 3.8 -1.12) (end 3.8 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 3.56 -1.12) (end 3.56 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start -1.05 -1.25) (end -1.05 1.25) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.25) (end 11.21 1.25) (layer F.CrtYd) (width 0.05))
(fp_line (start 11.21 1.25) (end 11.21 -1.25) (layer F.CrtYd) (width 0.05))
(fp_line (start 11.21 -1.25) (end -1.05 -1.25) (layer F.CrtYd) (width 0.05))
(fp_text user K (at 0 -1.8 90) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user K (at 0 -1.8 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 5.38 0 90) (layer F.Fab)
(effects (font (size 0.8 0.8) (thickness 0.12)))
)
(pad 2 thru_hole oval (at 10.16 0 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 14 "Net-(C113-Pad2)"))
(pad 1 thru_hole rect (at 0 0 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 3 GND))
(model ${KISYS3DMOD}/Diode_THT.3dshapes/D_DO-35_SOD27_P10.16mm_Horizontal.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Diode_THT:D_DO-35_SOD27_P10.16mm_Horizontal (layer F.Cu) (tedit 5AE50CD5) (tstamp 5FD6D65A)
(at 58.42 188.58 90)
(descr "Diode, DO-35_SOD27 series, Axial, Horizontal, pin pitch=10.16mm, , length*diameter=4*2mm^2, , http://www.diodes.com/_files/packages/DO-35.pdf")
(tags "Diode DO-35_SOD27 series Axial Horizontal pin pitch 10.16mm length 4mm diameter 2mm")
(path /5FF62030)
(fp_text reference D102 (at 5.08 -2.12 90) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 1N4148 (at 5.08 2.12 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 3.08 -1) (end 3.08 1) (layer F.Fab) (width 0.1))
(fp_line (start 3.08 1) (end 7.08 1) (layer F.Fab) (width 0.1))
(fp_line (start 7.08 1) (end 7.08 -1) (layer F.Fab) (width 0.1))
(fp_line (start 7.08 -1) (end 3.08 -1) (layer F.Fab) (width 0.1))
(fp_line (start 0 0) (end 3.08 0) (layer F.Fab) (width 0.1))
(fp_line (start 10.16 0) (end 7.08 0) (layer F.Fab) (width 0.1))
(fp_line (start 3.68 -1) (end 3.68 1) (layer F.Fab) (width 0.1))
(fp_line (start 3.78 -1) (end 3.78 1) (layer F.Fab) (width 0.1))
(fp_line (start 3.58 -1) (end 3.58 1) (layer F.Fab) (width 0.1))
(fp_line (start 2.96 -1.12) (end 2.96 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 2.96 1.12) (end 7.2 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 7.2 1.12) (end 7.2 -1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 7.2 -1.12) (end 2.96 -1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 1.04 0) (end 2.96 0) (layer F.SilkS) (width 0.12))
(fp_line (start 9.12 0) (end 7.2 0) (layer F.SilkS) (width 0.12))
(fp_line (start 3.68 -1.12) (end 3.68 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 3.8 -1.12) (end 3.8 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 3.56 -1.12) (end 3.56 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start -1.05 -1.25) (end -1.05 1.25) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.25) (end 11.21 1.25) (layer F.CrtYd) (width 0.05))
(fp_line (start 11.21 1.25) (end 11.21 -1.25) (layer F.CrtYd) (width 0.05))
(fp_line (start 11.21 -1.25) (end -1.05 -1.25) (layer F.CrtYd) (width 0.05))
(fp_text user K (at 0 -1.8 90) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user K (at 0 -1.8 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 5.38 0 90) (layer F.Fab)
(effects (font (size 0.8 0.8) (thickness 0.12)))
)
(pad 2 thru_hole oval (at 10.16 0 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 3 GND))
(pad 1 thru_hole rect (at 0 0 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 6 "Net-(C107-Pad2)"))
(model ${KISYS3DMOD}/Diode_THT.3dshapes/D_DO-35_SOD27_P10.16mm_Horizontal.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Diode_THT:D_DO-35_SOD27_P10.16mm_Horizontal (layer F.Cu) (tedit 5AE50CD5) (tstamp 5FD6D63B)
(at 60.96 178.42 270)
(descr "Diode, DO-35_SOD27 series, Axial, Horizontal, pin pitch=10.16mm, , length*diameter=4*2mm^2, , http://www.diodes.com/_files/packages/DO-35.pdf")
(tags "Diode DO-35_SOD27 series Axial Horizontal pin pitch 10.16mm length 4mm diameter 2mm")
(path /5FF619A0)
(fp_text reference D103 (at 5.08 -2.12 90) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 1N4148 (at 5.08 2.12 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
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(fp_line (start 7.08 -1) (end 3.08 -1) (layer F.Fab) (width 0.1))
(fp_line (start 0 0) (end 3.08 0) (layer F.Fab) (width 0.1))
(fp_line (start 10.16 0) (end 7.08 0) (layer F.Fab) (width 0.1))
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(fp_line (start 2.96 -1.12) (end 2.96 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 2.96 1.12) (end 7.2 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 7.2 1.12) (end 7.2 -1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 7.2 -1.12) (end 2.96 -1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 1.04 0) (end 2.96 0) (layer F.SilkS) (width 0.12))
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(fp_line (start 3.68 -1.12) (end 3.68 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 3.8 -1.12) (end 3.8 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 3.56 -1.12) (end 3.56 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start -1.05 -1.25) (end -1.05 1.25) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.25) (end 11.21 1.25) (layer F.CrtYd) (width 0.05))
(fp_line (start 11.21 1.25) (end 11.21 -1.25) (layer F.CrtYd) (width 0.05))
(fp_line (start 11.21 -1.25) (end -1.05 -1.25) (layer F.CrtYd) (width 0.05))
(fp_text user K (at 0 -1.8 90) (layer F.SilkS)
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(fp_text user K (at 0 -1.8 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 5.38 0 90) (layer F.Fab)
(effects (font (size 0.8 0.8) (thickness 0.12)))
)
(pad 2 thru_hole oval (at 10.16 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 6 "Net-(C107-Pad2)"))
(pad 1 thru_hole rect (at 0 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 3 GND))
(model ${KISYS3DMOD}/Diode_THT.3dshapes/D_DO-35_SOD27_P10.16mm_Horizontal.wrl
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(module Capacitor_THT:CP_Radial_D5.0mm_P2.00mm (layer F.Cu) (tedit 5AE50EF0) (tstamp 5FD6D12A)
(at 59.69 196.2)
(descr "CP, Radial series, Radial, pin pitch=2.00mm, , diameter=5mm, Electrolytic Capacitor")
(tags "CP Radial series Radial pin pitch 2.00mm diameter 5mm Electrolytic Capacitor")
(path /600A9821)
(fp_text reference C113 (at 1 -3.75) (layer F.SilkS)
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(fp_text value "1uF/ 63V" (at 1 3.75) (layer F.Fab)
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(fp_circle (center 1 0) (end 3.5 0) (layer F.Fab) (width 0.1))
(fp_circle (center 1 0) (end 3.62 0) (layer F.SilkS) (width 0.12))
(fp_circle (center 1 0) (end 3.75 0) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.133605 -1.0875) (end -0.633605 -1.0875) (layer F.Fab) (width 0.1))
(fp_line (start -0.883605 -1.3375) (end -0.883605 -0.8375) (layer F.Fab) (width 0.1))
(fp_line (start 1 1.04) (end 1 2.58) (layer F.SilkS) (width 0.12))
(fp_line (start 1 -2.58) (end 1 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 1.04 1.04) (end 1.04 2.58) (layer F.SilkS) (width 0.12))
(fp_line (start 1.04 -2.58) (end 1.04 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 1.08 -2.579) (end 1.08 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 1.08 1.04) (end 1.08 2.579) (layer F.SilkS) (width 0.12))
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(fp_line (start 1.12 1.04) (end 1.12 2.578) (layer F.SilkS) (width 0.12))
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(fp_line (start 1.24 1.04) (end 1.24 2.569) (layer F.SilkS) (width 0.12))
(fp_line (start 1.28 -2.565) (end 1.28 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 1.28 1.04) (end 1.28 2.565) (layer F.SilkS) (width 0.12))
(fp_line (start 1.32 -2.561) (end 1.32 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 1.32 1.04) (end 1.32 2.561) (layer F.SilkS) (width 0.12))
(fp_line (start 1.36 -2.556) (end 1.36 -1.04) (layer F.SilkS) (width 0.12))
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(fp_line (start 1.4 -2.55) (end 1.4 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 1.4 1.04) (end 1.4 2.55) (layer F.SilkS) (width 0.12))
(fp_line (start 1.44 -2.543) (end 1.44 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 1.44 1.04) (end 1.44 2.543) (layer F.SilkS) (width 0.12))
(fp_line (start 1.48 -2.536) (end 1.48 -1.04) (layer F.SilkS) (width 0.12))
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(fp_line (start 1.721 -2.48) (end 1.721 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 1.721 1.04) (end 1.721 2.48) (layer F.SilkS) (width 0.12))
(fp_line (start 1.761 -2.468) (end 1.761 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 1.761 1.04) (end 1.761 2.468) (layer F.SilkS) (width 0.12))
(fp_line (start 1.801 -2.455) (end 1.801 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 1.801 1.04) (end 1.801 2.455) (layer F.SilkS) (width 0.12))
(fp_line (start 1.841 -2.442) (end 1.841 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 1.841 1.04) (end 1.841 2.442) (layer F.SilkS) (width 0.12))
(fp_line (start 1.881 -2.428) (end 1.881 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 1.881 1.04) (end 1.881 2.428) (layer F.SilkS) (width 0.12))
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(fp_line (start 1.921 1.04) (end 1.921 2.414) (layer F.SilkS) (width 0.12))
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(fp_line (start 1.961 1.04) (end 1.961 2.398) (layer F.SilkS) (width 0.12))
(fp_line (start 2.001 -2.382) (end 2.001 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 2.001 1.04) (end 2.001 2.382) (layer F.SilkS) (width 0.12))
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(fp_line (start 2.041 1.04) (end 2.041 2.365) (layer F.SilkS) (width 0.12))
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(fp_line (start 2.081 1.04) (end 2.081 2.348) (layer F.SilkS) (width 0.12))
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(fp_line (start -1.804775 -1.475) (end -1.304775 -1.475) (layer F.SilkS) (width 0.12))
(fp_line (start -1.554775 -1.725) (end -1.554775 -1.225) (layer F.SilkS) (width 0.12))
(fp_text user %R (at 1 0) (layer F.Fab)
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(pad 2 thru_hole circle (at 2 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 14 "Net-(C113-Pad2)"))
(pad 1 thru_hole rect (at 0 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 15 "Net-(C113-Pad1)"))
(model ${KISYS3DMOD}/Capacitor_THT.3dshapes/CP_Radial_D5.0mm_P2.00mm.wrl
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(module Capacitor_THT:CP_Radial_D10.0mm_P5.00mm (layer F.Cu) (tedit 5AE50EF1) (tstamp 5FD6D0A7)
(at 66.04 206.36 90)
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
(descr "CP, Radial series, Radial, pin pitch=5.00mm, , diameter=10mm, Electrolytic Capacitor")
(tags "CP Radial series Radial pin pitch 5.00mm diameter 10mm Electrolytic Capacitor")
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(path /5FDD46AF)
(fp_text reference C111 (at 2.5 -6.25 90) (layer F.SilkS)
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(fp_text value "100uF/ 63V" (at 2.5 6.25 90) (layer F.Fab)
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_circle (center 2.5 0) (end 7.5 0) (layer F.Fab) (width 0.1))
(fp_circle (center 2.5 0) (end 7.62 0) (layer F.SilkS) (width 0.12))
(fp_circle (center 2.5 0) (end 7.75 0) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.788861 -2.1875) (end -0.788861 -2.1875) (layer F.Fab) (width 0.1))
(fp_line (start -1.288861 -2.6875) (end -1.288861 -1.6875) (layer F.Fab) (width 0.1))
(fp_line (start 2.5 -5.08) (end 2.5 5.08) (layer F.SilkS) (width 0.12))
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PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(fp_text user %R (at 2.5 0 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 2 thru_hole circle (at 5 0 90) (size 2 2) (drill 1) (layers *.Cu *.Mask)
(net 3 GND))
(pad 1 thru_hole rect (at 0 0 90) (size 2 2) (drill 1) (layers *.Cu *.Mask)
(net 12 V_Phant))
(model ${KISYS3DMOD}/Capacitor_THT.3dshapes/CP_Radial_D10.0mm_P5.00mm.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Capacitor_THT:CP_Radial_D5.0mm_P2.00mm (layer F.Cu) (tedit 5AE50EF0) (tstamp 5FD6CF13)
(at 64.77 188.58)
(descr "CP, Radial series, Radial, pin pitch=2.00mm, , diameter=5mm, Electrolytic Capacitor")
(tags "CP Radial series Radial pin pitch 2.00mm diameter 5mm Electrolytic Capacitor")
(path /5FF457A4)
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)
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)
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(fp_line (start 1.44 1.04) (end 1.44 2.543) (layer F.SilkS) (width 0.12))
(fp_line (start 1.48 -2.536) (end 1.48 -1.04) (layer F.SilkS) (width 0.12))
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(fp_line (start 1.52 -2.528) (end 1.52 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 1.52 1.04) (end 1.52 2.528) (layer F.SilkS) (width 0.12))
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(fp_line (start 1.56 1.04) (end 1.56 2.52) (layer F.SilkS) (width 0.12))
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(fp_line (start 1.6 1.04) (end 1.6 2.511) (layer F.SilkS) (width 0.12))
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(fp_line (start 1.64 1.04) (end 1.64 2.501) (layer F.SilkS) (width 0.12))
(fp_line (start 1.68 -2.491) (end 1.68 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 1.68 1.04) (end 1.68 2.491) (layer F.SilkS) (width 0.12))
(fp_line (start 1.721 -2.48) (end 1.721 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 1.721 1.04) (end 1.721 2.48) (layer F.SilkS) (width 0.12))
(fp_line (start 1.761 -2.468) (end 1.761 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 1.761 1.04) (end 1.761 2.468) (layer F.SilkS) (width 0.12))
(fp_line (start 1.801 -2.455) (end 1.801 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 1.801 1.04) (end 1.801 2.455) (layer F.SilkS) (width 0.12))
(fp_line (start 1.841 -2.442) (end 1.841 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 1.841 1.04) (end 1.841 2.442) (layer F.SilkS) (width 0.12))
(fp_line (start 1.881 -2.428) (end 1.881 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 1.881 1.04) (end 1.881 2.428) (layer F.SilkS) (width 0.12))
(fp_line (start 1.921 -2.414) (end 1.921 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 1.921 1.04) (end 1.921 2.414) (layer F.SilkS) (width 0.12))
(fp_line (start 1.961 -2.398) (end 1.961 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 1.961 1.04) (end 1.961 2.398) (layer F.SilkS) (width 0.12))
(fp_line (start 2.001 -2.382) (end 2.001 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 2.001 1.04) (end 2.001 2.382) (layer F.SilkS) (width 0.12))
(fp_line (start 2.041 -2.365) (end 2.041 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 2.041 1.04) (end 2.041 2.365) (layer F.SilkS) (width 0.12))
(fp_line (start 2.081 -2.348) (end 2.081 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 2.081 1.04) (end 2.081 2.348) (layer F.SilkS) (width 0.12))
(fp_line (start 2.121 -2.329) (end 2.121 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 2.121 1.04) (end 2.121 2.329) (layer F.SilkS) (width 0.12))
(fp_line (start 2.161 -2.31) (end 2.161 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 2.161 1.04) (end 2.161 2.31) (layer F.SilkS) (width 0.12))
(fp_line (start 2.201 -2.29) (end 2.201 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 2.201 1.04) (end 2.201 2.29) (layer F.SilkS) (width 0.12))
(fp_line (start 2.241 -2.268) (end 2.241 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 2.241 1.04) (end 2.241 2.268) (layer F.SilkS) (width 0.12))
(fp_line (start 2.281 -2.247) (end 2.281 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 2.281 1.04) (end 2.281 2.247) (layer F.SilkS) (width 0.12))
(fp_line (start 2.321 -2.224) (end 2.321 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 2.321 1.04) (end 2.321 2.224) (layer F.SilkS) (width 0.12))
(fp_line (start 2.361 -2.2) (end 2.361 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 2.361 1.04) (end 2.361 2.2) (layer F.SilkS) (width 0.12))
(fp_line (start 2.401 -2.175) (end 2.401 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 2.401 1.04) (end 2.401 2.175) (layer F.SilkS) (width 0.12))
(fp_line (start 2.441 -2.149) (end 2.441 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 2.441 1.04) (end 2.441 2.149) (layer F.SilkS) (width 0.12))
(fp_line (start 2.481 -2.122) (end 2.481 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 2.481 1.04) (end 2.481 2.122) (layer F.SilkS) (width 0.12))
(fp_line (start 2.521 -2.095) (end 2.521 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 2.521 1.04) (end 2.521 2.095) (layer F.SilkS) (width 0.12))
(fp_line (start 2.561 -2.065) (end 2.561 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 2.561 1.04) (end 2.561 2.065) (layer F.SilkS) (width 0.12))
(fp_line (start 2.601 -2.035) (end 2.601 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 2.601 1.04) (end 2.601 2.035) (layer F.SilkS) (width 0.12))
(fp_line (start 2.641 -2.004) (end 2.641 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 2.641 1.04) (end 2.641 2.004) (layer F.SilkS) (width 0.12))
(fp_line (start 2.681 -1.971) (end 2.681 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 2.681 1.04) (end 2.681 1.971) (layer F.SilkS) (width 0.12))
(fp_line (start 2.721 -1.937) (end 2.721 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 2.721 1.04) (end 2.721 1.937) (layer F.SilkS) (width 0.12))
(fp_line (start 2.761 -1.901) (end 2.761 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 2.761 1.04) (end 2.761 1.901) (layer F.SilkS) (width 0.12))
(fp_line (start 2.801 -1.864) (end 2.801 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 2.801 1.04) (end 2.801 1.864) (layer F.SilkS) (width 0.12))
(fp_line (start 2.841 -1.826) (end 2.841 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 2.841 1.04) (end 2.841 1.826) (layer F.SilkS) (width 0.12))
(fp_line (start 2.881 -1.785) (end 2.881 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 2.881 1.04) (end 2.881 1.785) (layer F.SilkS) (width 0.12))
(fp_line (start 2.921 -1.743) (end 2.921 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 2.921 1.04) (end 2.921 1.743) (layer F.SilkS) (width 0.12))
(fp_line (start 2.961 -1.699) (end 2.961 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 2.961 1.04) (end 2.961 1.699) (layer F.SilkS) (width 0.12))
(fp_line (start 3.001 -1.653) (end 3.001 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 3.001 1.04) (end 3.001 1.653) (layer F.SilkS) (width 0.12))
(fp_line (start 3.041 -1.605) (end 3.041 1.605) (layer F.SilkS) (width 0.12))
(fp_line (start 3.081 -1.554) (end 3.081 1.554) (layer F.SilkS) (width 0.12))
(fp_line (start 3.121 -1.5) (end 3.121 1.5) (layer F.SilkS) (width 0.12))
(fp_line (start 3.161 -1.443) (end 3.161 1.443) (layer F.SilkS) (width 0.12))
(fp_line (start 3.201 -1.383) (end 3.201 1.383) (layer F.SilkS) (width 0.12))
(fp_line (start 3.241 -1.319) (end 3.241 1.319) (layer F.SilkS) (width 0.12))
(fp_line (start 3.281 -1.251) (end 3.281 1.251) (layer F.SilkS) (width 0.12))
(fp_line (start 3.321 -1.178) (end 3.321 1.178) (layer F.SilkS) (width 0.12))
(fp_line (start 3.361 -1.098) (end 3.361 1.098) (layer F.SilkS) (width 0.12))
(fp_line (start 3.401 -1.011) (end 3.401 1.011) (layer F.SilkS) (width 0.12))
(fp_line (start 3.441 -0.915) (end 3.441 0.915) (layer F.SilkS) (width 0.12))
(fp_line (start 3.481 -0.805) (end 3.481 0.805) (layer F.SilkS) (width 0.12))
(fp_line (start 3.521 -0.677) (end 3.521 0.677) (layer F.SilkS) (width 0.12))
(fp_line (start 3.561 -0.518) (end 3.561 0.518) (layer F.SilkS) (width 0.12))
(fp_line (start 3.601 -0.284) (end 3.601 0.284) (layer F.SilkS) (width 0.12))
(fp_line (start -1.804775 -1.475) (end -1.304775 -1.475) (layer F.SilkS) (width 0.12))
(fp_line (start -1.554775 -1.725) (end -1.554775 -1.225) (layer F.SilkS) (width 0.12))
(fp_text user %R (at 1 0) (layer F.Fab)
Schematic: Bugfixes, VU meter draft, first development PCB draft
2020-11-02 00:00:47 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(pad 2 thru_hole circle (at 2 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 6 "Net-(C107-Pad2)"))
(pad 1 thru_hole rect (at 0 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 7 "Net-(C107-Pad1)"))
(model ${KISYS3DMOD}/Capacitor_THT.3dshapes/CP_Radial_D5.0mm_P2.00mm.wrl
Schematic: Bugfixes, VU meter draft, first development PCB draft
2020-11-02 00:00:47 +00:00
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(module Resistor_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal (layer F.Cu) (tedit 5AE5139B) (tstamp 5FD6BBAC)
(at 86.36 139.7 270)
(descr "Resistor, Axial_DIN0207 series, Axial, Horizontal, pin pitch=10.16mm, 0.25W = 1/4W, length*diameter=6.3*2.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf")
(tags "Resistor Axial_DIN0207 series Axial Horizontal pin pitch 10.16mm 0.25W = 1/4W length 6.3mm diameter 2.5mm")
(path /6021952F)
(fp_text reference R119 (at 5.08 -2.37 90) (layer F.SilkS)
Schematic: Bugfixes, VU meter draft, first development PCB draft
2020-11-02 00:00:47 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(fp_text value 22K (at 5.08 2.37 90) (layer F.Fab)
Schematic: Bugfixes, VU meter draft, first development PCB draft
2020-11-02 00:00:47 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(fp_line (start 11.21 -1.5) (end -1.05 -1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 11.21 1.5) (end 11.21 -1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.5) (end 11.21 1.5) (layer F.CrtYd) (width 0.05))
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
(fp_line (start -1.05 -1.5) (end -1.05 1.5) (layer F.CrtYd) (width 0.05))
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(fp_line (start 9.12 0) (end 8.35 0) (layer F.SilkS) (width 0.12))
(fp_line (start 1.04 0) (end 1.81 0) (layer F.SilkS) (width 0.12))
(fp_line (start 8.35 -1.37) (end 1.81 -1.37) (layer F.SilkS) (width 0.12))
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(fp_line (start 1.81 1.37) (end 8.35 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 1.81 -1.37) (end 1.81 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 10.16 0) (end 8.23 0) (layer F.Fab) (width 0.1))
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(fp_line (start 1.93 1.25) (end 8.23 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 1.93 -1.25) (end 1.93 1.25) (layer F.Fab) (width 0.1))
(fp_text user %R (at 5.08 0 90) (layer F.Fab)
Schematic: Bugfixes, VU meter draft, first development PCB draft
2020-11-02 00:00:47 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(pad 2 thru_hole oval (at 10.16 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 50 "Net-(R119-Pad2)"))
final fixes for first prototype PCB order
2020-11-12 23:40:18 +00:00
(pad 1 thru_hole circle (at 0 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(net 4 "Net-(C103-Pad2)"))
(model ${KISYS3DMOD}/Resistor_THT.3dshapes/R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal.wrl
Schematic: Bugfixes, VU meter draft, first development PCB draft
2020-11-02 00:00:47 +00:00
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(module Resistor_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal (layer F.Cu) (tedit 5AE5139B) (tstamp 5FD6BB95)
(at 91.44 139.7 270)
(descr "Resistor, Axial_DIN0207 series, Axial, Horizontal, pin pitch=10.16mm, 0.25W = 1/4W, length*diameter=6.3*2.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf")
(tags "Resistor Axial_DIN0207 series Axial Horizontal pin pitch 10.16mm 0.25W = 1/4W length 6.3mm diameter 2.5mm")
(path /60218A82)
(fp_text reference R117 (at 5.08 -2.37 90) (layer F.SilkS)
Schematic: Bugfixes, VU meter draft, first development PCB draft
2020-11-02 00:00:47 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(fp_text value 22K (at 5.08 2.37 90) (layer F.Fab)
Schematic: Bugfixes, VU meter draft, first development PCB draft
2020-11-02 00:00:47 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(fp_line (start 11.21 -1.5) (end -1.05 -1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 11.21 1.5) (end 11.21 -1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.5) (end 11.21 1.5) (layer F.CrtYd) (width 0.05))
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
(fp_line (start -1.05 -1.5) (end -1.05 1.5) (layer F.CrtYd) (width 0.05))
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(fp_line (start 9.12 0) (end 8.35 0) (layer F.SilkS) (width 0.12))
(fp_line (start 1.04 0) (end 1.81 0) (layer F.SilkS) (width 0.12))
(fp_line (start 8.35 -1.37) (end 1.81 -1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 8.35 1.37) (end 8.35 -1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 1.81 1.37) (end 8.35 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 1.81 -1.37) (end 1.81 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 10.16 0) (end 8.23 0) (layer F.Fab) (width 0.1))
(fp_line (start 0 0) (end 1.93 0) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 -1.25) (end 1.93 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 1.25) (end 8.23 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 1.93 1.25) (end 8.23 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 1.93 -1.25) (end 1.93 1.25) (layer F.Fab) (width 0.1))
(fp_text user %R (at 5.08 0 90) (layer F.Fab)
Schematic: Bugfixes, VU meter draft, first development PCB draft
2020-11-02 00:00:47 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(pad 2 thru_hole oval (at 10.16 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 48 "Net-(R117-Pad2)"))
(pad 1 thru_hole circle (at 0 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 4 "Net-(C103-Pad2)"))
(model ${KISYS3DMOD}/Resistor_THT.3dshapes/R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal.wrl
Schematic: Bugfixes, VU meter draft, first development PCB draft
2020-11-02 00:00:47 +00:00
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(module Resistor_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal (layer F.Cu) (tedit 5AE5139B) (tstamp 5FD6BB7E)
(at 80.01 139.7 270)
(descr "Resistor, Axial_DIN0207 series, Axial, Horizontal, pin pitch=10.16mm, 0.25W = 1/4W, length*diameter=6.3*2.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf")
(tags "Resistor Axial_DIN0207 series Axial Horizontal pin pitch 10.16mm 0.25W = 1/4W length 6.3mm diameter 2.5mm")
(path /601F3758)
(fp_text reference R108 (at 5.08 -2.37 90) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 22K (at 5.08 2.37 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 11.21 -1.5) (end -1.05 -1.5) (layer F.CrtYd) (width 0.05))
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(fp_line (start 1.81 1.37) (end 8.35 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 1.81 -1.37) (end 1.81 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 10.16 0) (end 8.23 0) (layer F.Fab) (width 0.1))
(fp_line (start 0 0) (end 1.93 0) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 -1.25) (end 1.93 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 1.25) (end 8.23 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 1.93 1.25) (end 8.23 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 1.93 -1.25) (end 1.93 1.25) (layer F.Fab) (width 0.1))
(fp_text user %R (at 5.08 0 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 2 thru_hole oval (at 10.16 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 45 "Net-(R108-Pad2)"))
(pad 1 thru_hole circle (at 0 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 4 "Net-(C103-Pad2)"))
(model ${KISYS3DMOD}/Resistor_THT.3dshapes/R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Resistor_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal (layer F.Cu) (tedit 5AE5139B) (tstamp 5FD6BB67)
(at 73.66 139.7 270)
(descr "Resistor, Axial_DIN0207 series, Axial, Horizontal, pin pitch=10.16mm, 0.25W = 1/4W, length*diameter=6.3*2.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf")
(tags "Resistor Axial_DIN0207 series Axial Horizontal pin pitch 10.16mm 0.25W = 1/4W length 6.3mm diameter 2.5mm")
(path /5FFA3C32)
(fp_text reference R101 (at 5.08 -2.37 90) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 22K (at 5.08 2.37 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 11.21 -1.5) (end -1.05 -1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 11.21 1.5) (end 11.21 -1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.5) (end 11.21 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 -1.5) (end -1.05 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 9.12 0) (end 8.35 0) (layer F.SilkS) (width 0.12))
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(fp_text user %R (at 5.08 0 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
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(net 42 "Net-(R101-Pad2)"))
(pad 1 thru_hole circle (at 0 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 4 "Net-(C103-Pad2)"))
(model ${KISYS3DMOD}/Resistor_THT.3dshapes/R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Resistor_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal (layer F.Cu) (tedit 5AE5139B) (tstamp 5FD6BB50)
(at 107.95 221.6 90)
(descr "Resistor, Axial_DIN0207 series, Axial, Horizontal, pin pitch=10.16mm, 0.25W = 1/4W, length*diameter=6.3*2.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf")
(tags "Resistor Axial_DIN0207 series Axial Horizontal pin pitch 10.16mm 0.25W = 1/4W length 6.3mm diameter 2.5mm")
(path /5FF18A7E)
(fp_text reference R118 (at 5.08 -2.37 90) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 2.2K (at 5.08 2.37 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 11.21 -1.5) (end -1.05 -1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 11.21 1.5) (end 11.21 -1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.5) (end 11.21 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 -1.5) (end -1.05 1.5) (layer F.CrtYd) (width 0.05))
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(fp_line (start 10.16 0) (end 8.23 0) (layer F.Fab) (width 0.1))
(fp_line (start 0 0) (end 1.93 0) (layer F.Fab) (width 0.1))
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(fp_line (start 1.93 -1.25) (end 1.93 1.25) (layer F.Fab) (width 0.1))
(fp_text user %R (at 5.08 0 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 2 thru_hole oval (at 10.16 0 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 3 GND))
(pad 1 thru_hole circle (at 0 0 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 49 "Net-(R118-Pad1)"))
(model ${KISYS3DMOD}/Resistor_THT.3dshapes/R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Capacitor_THT:CP_Radial_D5.0mm_P2.00mm (layer F.Cu) (tedit 5AE50EF0) (tstamp 5F9FD678)
(at 114.3 221.6 90)
(descr "CP, Radial series, Radial, pin pitch=2.00mm, , diameter=5mm, Electrolytic Capacitor")
(tags "CP Radial series Radial pin pitch 2.00mm diameter 5mm Electrolytic Capacitor")
(path /5FFF6761)
(fp_text reference C114 (at 1 -3.75 90) (layer F.SilkS)
Schematic: Bugfixes, VU meter draft, first development PCB draft
2020-11-02 00:00:47 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(fp_text value 1uF (at 1 3.75 90) (layer F.Fab)
Schematic: Bugfixes, VU meter draft, first development PCB draft
2020-11-02 00:00:47 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
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(fp_line (start 1 -2.58) (end 1 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 1 1.04) (end 1 2.58) (layer F.SilkS) (width 0.12))
(fp_line (start -0.883605 -1.3375) (end -0.883605 -0.8375) (layer F.Fab) (width 0.1))
(fp_line (start -1.133605 -1.0875) (end -0.633605 -1.0875) (layer F.Fab) (width 0.1))
(fp_circle (center 1 0) (end 3.75 0) (layer F.CrtYd) (width 0.05))
(fp_circle (center 1 0) (end 3.62 0) (layer F.SilkS) (width 0.12))
(fp_circle (center 1 0) (end 3.5 0) (layer F.Fab) (width 0.1))
(fp_text user %R (at 1 0 90) (layer F.Fab)
Schematic: Bugfixes, VU meter draft, first development PCB draft
2020-11-02 00:00:47 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(pad 2 thru_hole circle (at 2 0 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 16 "Net-(C114-Pad2)"))
(pad 1 thru_hole rect (at 0 0 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 17 "Net-(C114-Pad1)"))
(model ${KISYS3DMOD}/Capacitor_THT.3dshapes/CP_Radial_D5.0mm_P2.00mm.wrl
Schematic: Bugfixes, VU meter draft, first development PCB draft
2020-11-02 00:00:47 +00:00
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
Move VU-Meter to own project
2020-11-09 00:52:43 +00:00
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(module Capacitor_THT:CP_Radial_D5.0mm_P2.00mm (layer F.Cu) (tedit 5AE50EF0) (tstamp 5F9FD663)
(at 101.6 195.47 270)
(descr "CP, Radial series, Radial, pin pitch=2.00mm, , diameter=5mm, Electrolytic Capacitor")
(tags "CP Radial series Radial pin pitch 2.00mm diameter 5mm Electrolytic Capacitor")
(path /5F864500)
(fp_text reference C109 (at 1 -3.75 90) (layer F.SilkS)
Move VU-Meter to own project
2020-11-09 00:52:43 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(fp_text value 1uF (at 1 3.75 90) (layer F.Fab)
Move VU-Meter to own project
2020-11-09 00:52:43 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(fp_line (start -1.554775 -1.725) (end -1.554775 -1.225) (layer F.SilkS) (width 0.12))
(fp_line (start -1.804775 -1.475) (end -1.304775 -1.475) (layer F.SilkS) (width 0.12))
(fp_line (start 3.601 -0.284) (end 3.601 0.284) (layer F.SilkS) (width 0.12))
(fp_line (start 3.561 -0.518) (end 3.561 0.518) (layer F.SilkS) (width 0.12))
(fp_line (start 3.521 -0.677) (end 3.521 0.677) (layer F.SilkS) (width 0.12))
(fp_line (start 3.481 -0.805) (end 3.481 0.805) (layer F.SilkS) (width 0.12))
(fp_line (start 3.441 -0.915) (end 3.441 0.915) (layer F.SilkS) (width 0.12))
(fp_line (start 3.401 -1.011) (end 3.401 1.011) (layer F.SilkS) (width 0.12))
(fp_line (start 3.361 -1.098) (end 3.361 1.098) (layer F.SilkS) (width 0.12))
(fp_line (start 3.321 -1.178) (end 3.321 1.178) (layer F.SilkS) (width 0.12))
(fp_line (start 3.281 -1.251) (end 3.281 1.251) (layer F.SilkS) (width 0.12))
(fp_line (start 3.241 -1.319) (end 3.241 1.319) (layer F.SilkS) (width 0.12))
(fp_line (start 3.201 -1.383) (end 3.201 1.383) (layer F.SilkS) (width 0.12))
(fp_line (start 3.161 -1.443) (end 3.161 1.443) (layer F.SilkS) (width 0.12))
(fp_line (start 3.121 -1.5) (end 3.121 1.5) (layer F.SilkS) (width 0.12))
(fp_line (start 3.081 -1.554) (end 3.081 1.554) (layer F.SilkS) (width 0.12))
(fp_line (start 3.041 -1.605) (end 3.041 1.605) (layer F.SilkS) (width 0.12))
(fp_line (start 3.001 1.04) (end 3.001 1.653) (layer F.SilkS) (width 0.12))
(fp_line (start 3.001 -1.653) (end 3.001 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 2.961 1.04) (end 2.961 1.699) (layer F.SilkS) (width 0.12))
(fp_line (start 2.961 -1.699) (end 2.961 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 2.921 1.04) (end 2.921 1.743) (layer F.SilkS) (width 0.12))
(fp_line (start 2.921 -1.743) (end 2.921 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 2.881 1.04) (end 2.881 1.785) (layer F.SilkS) (width 0.12))
(fp_line (start 2.881 -1.785) (end 2.881 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 2.841 1.04) (end 2.841 1.826) (layer F.SilkS) (width 0.12))
(fp_line (start 2.841 -1.826) (end 2.841 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 2.801 1.04) (end 2.801 1.864) (layer F.SilkS) (width 0.12))
(fp_line (start 2.801 -1.864) (end 2.801 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 2.761 1.04) (end 2.761 1.901) (layer F.SilkS) (width 0.12))
(fp_line (start 2.761 -1.901) (end 2.761 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 2.721 1.04) (end 2.721 1.937) (layer F.SilkS) (width 0.12))
(fp_line (start 2.721 -1.937) (end 2.721 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 2.681 1.04) (end 2.681 1.971) (layer F.SilkS) (width 0.12))
(fp_line (start 2.681 -1.971) (end 2.681 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 2.641 1.04) (end 2.641 2.004) (layer F.SilkS) (width 0.12))
(fp_line (start 2.641 -2.004) (end 2.641 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 2.601 1.04) (end 2.601 2.035) (layer F.SilkS) (width 0.12))
(fp_line (start 2.601 -2.035) (end 2.601 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 2.561 1.04) (end 2.561 2.065) (layer F.SilkS) (width 0.12))
(fp_line (start 2.561 -2.065) (end 2.561 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 2.521 1.04) (end 2.521 2.095) (layer F.SilkS) (width 0.12))
(fp_line (start 2.521 -2.095) (end 2.521 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 2.481 1.04) (end 2.481 2.122) (layer F.SilkS) (width 0.12))
(fp_line (start 2.481 -2.122) (end 2.481 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 2.441 1.04) (end 2.441 2.149) (layer F.SilkS) (width 0.12))
(fp_line (start 2.441 -2.149) (end 2.441 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 2.401 1.04) (end 2.401 2.175) (layer F.SilkS) (width 0.12))
(fp_line (start 2.401 -2.175) (end 2.401 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 2.361 1.04) (end 2.361 2.2) (layer F.SilkS) (width 0.12))
(fp_line (start 2.361 -2.2) (end 2.361 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 2.321 1.04) (end 2.321 2.224) (layer F.SilkS) (width 0.12))
(fp_line (start 2.321 -2.224) (end 2.321 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 2.281 1.04) (end 2.281 2.247) (layer F.SilkS) (width 0.12))
(fp_line (start 2.281 -2.247) (end 2.281 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 2.241 1.04) (end 2.241 2.268) (layer F.SilkS) (width 0.12))
(fp_line (start 2.241 -2.268) (end 2.241 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 2.201 1.04) (end 2.201 2.29) (layer F.SilkS) (width 0.12))
(fp_line (start 2.201 -2.29) (end 2.201 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 2.161 1.04) (end 2.161 2.31) (layer F.SilkS) (width 0.12))
(fp_line (start 2.161 -2.31) (end 2.161 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 2.121 1.04) (end 2.121 2.329) (layer F.SilkS) (width 0.12))
(fp_line (start 2.121 -2.329) (end 2.121 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 2.081 1.04) (end 2.081 2.348) (layer F.SilkS) (width 0.12))
(fp_line (start 2.081 -2.348) (end 2.081 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 2.041 1.04) (end 2.041 2.365) (layer F.SilkS) (width 0.12))
(fp_line (start 2.041 -2.365) (end 2.041 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 2.001 1.04) (end 2.001 2.382) (layer F.SilkS) (width 0.12))
(fp_line (start 2.001 -2.382) (end 2.001 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 1.961 1.04) (end 1.961 2.398) (layer F.SilkS) (width 0.12))
(fp_line (start 1.961 -2.398) (end 1.961 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 1.921 1.04) (end 1.921 2.414) (layer F.SilkS) (width 0.12))
(fp_line (start 1.921 -2.414) (end 1.921 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 1.881 1.04) (end 1.881 2.428) (layer F.SilkS) (width 0.12))
(fp_line (start 1.881 -2.428) (end 1.881 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 1.841 1.04) (end 1.841 2.442) (layer F.SilkS) (width 0.12))
(fp_line (start 1.841 -2.442) (end 1.841 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 1.801 1.04) (end 1.801 2.455) (layer F.SilkS) (width 0.12))
(fp_line (start 1.801 -2.455) (end 1.801 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 1.761 1.04) (end 1.761 2.468) (layer F.SilkS) (width 0.12))
(fp_line (start 1.761 -2.468) (end 1.761 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 1.721 1.04) (end 1.721 2.48) (layer F.SilkS) (width 0.12))
(fp_line (start 1.721 -2.48) (end 1.721 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 1.68 1.04) (end 1.68 2.491) (layer F.SilkS) (width 0.12))
(fp_line (start 1.68 -2.491) (end 1.68 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 1.64 1.04) (end 1.64 2.501) (layer F.SilkS) (width 0.12))
(fp_line (start 1.64 -2.501) (end 1.64 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 1.6 1.04) (end 1.6 2.511) (layer F.SilkS) (width 0.12))
(fp_line (start 1.6 -2.511) (end 1.6 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 1.56 1.04) (end 1.56 2.52) (layer F.SilkS) (width 0.12))
(fp_line (start 1.56 -2.52) (end 1.56 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 1.52 1.04) (end 1.52 2.528) (layer F.SilkS) (width 0.12))
(fp_line (start 1.52 -2.528) (end 1.52 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 1.48 1.04) (end 1.48 2.536) (layer F.SilkS) (width 0.12))
(fp_line (start 1.48 -2.536) (end 1.48 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 1.44 1.04) (end 1.44 2.543) (layer F.SilkS) (width 0.12))
(fp_line (start 1.44 -2.543) (end 1.44 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 1.4 1.04) (end 1.4 2.55) (layer F.SilkS) (width 0.12))
(fp_line (start 1.4 -2.55) (end 1.4 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 1.36 1.04) (end 1.36 2.556) (layer F.SilkS) (width 0.12))
(fp_line (start 1.36 -2.556) (end 1.36 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 1.32 1.04) (end 1.32 2.561) (layer F.SilkS) (width 0.12))
(fp_line (start 1.32 -2.561) (end 1.32 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 1.28 1.04) (end 1.28 2.565) (layer F.SilkS) (width 0.12))
(fp_line (start 1.28 -2.565) (end 1.28 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 1.24 1.04) (end 1.24 2.569) (layer F.SilkS) (width 0.12))
(fp_line (start 1.24 -2.569) (end 1.24 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 1.2 1.04) (end 1.2 2.573) (layer F.SilkS) (width 0.12))
(fp_line (start 1.2 -2.573) (end 1.2 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 1.16 1.04) (end 1.16 2.576) (layer F.SilkS) (width 0.12))
(fp_line (start 1.16 -2.576) (end 1.16 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 1.12 1.04) (end 1.12 2.578) (layer F.SilkS) (width 0.12))
(fp_line (start 1.12 -2.578) (end 1.12 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 1.08 1.04) (end 1.08 2.579) (layer F.SilkS) (width 0.12))
(fp_line (start 1.08 -2.579) (end 1.08 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 1.04 -2.58) (end 1.04 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 1.04 1.04) (end 1.04 2.58) (layer F.SilkS) (width 0.12))
(fp_line (start 1 -2.58) (end 1 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 1 1.04) (end 1 2.58) (layer F.SilkS) (width 0.12))
(fp_line (start -0.883605 -1.3375) (end -0.883605 -0.8375) (layer F.Fab) (width 0.1))
(fp_line (start -1.133605 -1.0875) (end -0.633605 -1.0875) (layer F.Fab) (width 0.1))
(fp_circle (center 1 0) (end 3.75 0) (layer F.CrtYd) (width 0.05))
(fp_circle (center 1 0) (end 3.62 0) (layer F.SilkS) (width 0.12))
(fp_circle (center 1 0) (end 3.5 0) (layer F.Fab) (width 0.1))
(fp_text user %R (at 1 0 90) (layer F.Fab)
Schematic: Bugfixes, VU meter draft, first development PCB draft
2020-11-02 00:00:47 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(pad 2 thru_hole circle (at 2 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 77 MicPreOut))
(pad 1 thru_hole rect (at 0 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 9 "Net-(C109-Pad1)"))
(model ${KISYS3DMOD}/Capacitor_THT.3dshapes/CP_Radial_D5.0mm_P2.00mm.wrl
Schematic: Bugfixes, VU meter draft, first development PCB draft
2020-11-02 00:00:47 +00:00
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(module Capacitor_THT:C_Disc_D5.0mm_W2.5mm_P5.00mm (layer F.Cu) (tedit 5AE50EF0) (tstamp 5F9FD56D)
(at 68.58 135.89)
final fixes for first prototype PCB order
2020-11-12 23:40:18 +00:00
(descr "C, Disc series, Radial, pin pitch=5.00mm, , diameter*width=5*2.5mm^2, Capacitor, http://cdn-reichelt.de/documents/datenblatt/B300/DS_KERKO_TC.pdf")
(tags "C Disc series Radial pin pitch 5.00mm diameter 5mm width 2.5mm Capacitor")
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(path /5FFF675B)
(fp_text reference C103 (at 2.5 -2.5) (layer F.SilkS)
Schematic: Bugfixes, VU meter draft, first development PCB draft
2020-11-02 00:00:47 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(fp_text value 22pF (at 2.5 2.5) (layer F.Fab)
Schematic: Bugfixes, VU meter draft, first development PCB draft
2020-11-02 00:00:47 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
final fixes for first prototype PCB order
2020-11-12 23:40:18 +00:00
(fp_line (start 0 -1.25) (end 0 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 0 1.25) (end 5 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 5 1.25) (end 5 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 5 -1.25) (end 0 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start -0.12 -1.37) (end 5.12 -1.37) (layer F.SilkS) (width 0.12))
(fp_line (start -0.12 1.37) (end 5.12 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start -0.12 -1.37) (end -0.12 -1.055) (layer F.SilkS) (width 0.12))
(fp_line (start -0.12 1.055) (end -0.12 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 5.12 -1.37) (end 5.12 -1.055) (layer F.SilkS) (width 0.12))
(fp_line (start 5.12 1.055) (end 5.12 1.37) (layer F.SilkS) (width 0.12))
Schematic: Bugfixes, VU meter draft, first development PCB draft
2020-11-02 00:00:47 +00:00
(fp_line (start -1.05 -1.5) (end -1.05 1.5) (layer F.CrtYd) (width 0.05))
final fixes for first prototype PCB order
2020-11-12 23:40:18 +00:00
(fp_line (start -1.05 1.5) (end 6.05 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 6.05 1.5) (end 6.05 -1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 6.05 -1.5) (end -1.05 -1.5) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 2.5 0) (layer F.Fab)
Schematic: Bugfixes, VU meter draft, first development PCB draft
2020-11-02 00:00:47 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
final fixes for first prototype PCB order
2020-11-12 23:40:18 +00:00
(pad 2 thru_hole circle (at 5 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(net 4 "Net-(C103-Pad2)"))
(pad 1 thru_hole circle (at 0 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 76 SumOut))
final fixes for first prototype PCB order
2020-11-12 23:40:18 +00:00
(model ${KISYS3DMOD}/Capacitor_THT.3dshapes/C_Disc_D5.0mm_W2.5mm_P5.00mm.wrl
Schematic: Bugfixes, VU meter draft, first development PCB draft
2020-11-02 00:00:47 +00:00
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(module TestPoint:TestPoint_THTPad_D2.0mm_Drill1.0mm (layer F.Cu) (tedit 5A0F774F) (tstamp 5FACCD7A)
(at 68.58 142.24)
(descr "THT pad as test Point, diameter 2.0mm, hole diameter 1.0mm")
(tags "test point THT pad")
(path /5FC8A1ED)
(attr virtual)
(fp_text reference TP104 (at 0 -1.998) (layer F.SilkS)
Schematic: Bugfixes, VU meter draft, first development PCB draft
2020-11-02 00:00:47 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(fp_text value MicB (at 0 2.05) (layer F.SilkS)
Schematic: Bugfixes, VU meter draft, first development PCB draft
2020-11-02 00:00:47 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(fp_circle (center 0 0) (end 1.5 0) (layer F.CrtYd) (width 0.05))
(fp_circle (center 0 0) (end 0 1.2) (layer F.SilkS) (width 0.12))
(fp_text user %R (at 0 -2) (layer F.Fab)
Schematic: Bugfixes, VU meter draft, first development PCB draft
2020-11-02 00:00:47 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(pad 1 thru_hole circle (at 0 0) (size 2 2) (drill 1) (layers *.Cu *.Mask)
(net 39 /Monitor_OthersB))
Schematic: Bugfixes, VU meter draft, first development PCB draft
2020-11-02 00:00:47 +00:00
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(module TestPoint:TestPoint_THTPad_D2.0mm_Drill1.0mm (layer F.Cu) (tedit 5A0F774F) (tstamp 5FACCD72)
(at 63.5 146.05)
(descr "THT pad as test Point, diameter 2.0mm, hole diameter 1.0mm")
(tags "test point THT pad")
(path /5FC89B55)
(attr virtual)
(fp_text reference TP103 (at 0 -1.998) (layer F.SilkS)
Schematic: Bugfixes, VU meter draft, first development PCB draft
2020-11-02 00:00:47 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(fp_text value MicA (at 0 2.05) (layer F.SilkS)
Schematic: Bugfixes, VU meter draft, first development PCB draft
2020-11-02 00:00:47 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(fp_circle (center 0 0) (end 1.5 0) (layer F.CrtYd) (width 0.05))
(fp_circle (center 0 0) (end 0 1.2) (layer F.SilkS) (width 0.12))
(fp_text user %R (at 0 -2) (layer F.Fab)
Schematic: Bugfixes, VU meter draft, first development PCB draft
2020-11-02 00:00:47 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(pad 1 thru_hole circle (at 0 0) (size 2 2) (drill 1) (layers *.Cu *.Mask)
(net 40 /Monitor_OthersA))
Schematic: Bugfixes, VU meter draft, first development PCB draft
2020-11-02 00:00:47 +00:00
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(module TestPoint:TestPoint_THTPad_D2.0mm_Drill1.0mm (layer F.Cu) (tedit 5A0F774F) (tstamp 5FACCD6A)
(at 58.42 99.06 180)
(descr "THT pad as test Point, diameter 2.0mm, hole diameter 1.0mm")
(tags "test point THT pad")
(path /5FC89275)
(attr virtual)
(fp_text reference TP102 (at 0 -1.998) (layer F.SilkS)
Schematic: Bugfixes, VU meter draft, first development PCB draft
2020-11-02 00:00:47 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(fp_text value MicX (at 0 2.05) (layer F.Fab)
Schematic: Bugfixes, VU meter draft, first development PCB draft
2020-11-02 00:00:47 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(fp_circle (center 0 0) (end 1.5 0) (layer F.CrtYd) (width 0.05))
(fp_circle (center 0 0) (end 0 1.2) (layer F.SilkS) (width 0.12))
(fp_text user %R (at 0 -2) (layer F.Fab)
Schematic: Bugfixes, VU meter draft, first development PCB draft
2020-11-02 00:00:47 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(pad 1 thru_hole circle (at 0 0 180) (size 2 2) (drill 1) (layers *.Cu *.Mask)
(net 75 /PreampOut))
Schematic: Bugfixes, VU meter draft, first development PCB draft
2020-11-02 00:00:47 +00:00
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(module TestPoint:TestPoint_THTPad_D2.0mm_Drill1.0mm (layer F.Cu) (tedit 5A0F774F) (tstamp 5FACCD62)
(at 68.58 149.86)
(descr "THT pad as test Point, diameter 2.0mm, hole diameter 1.0mm")
(tags "test point THT pad")
(path /5FC8AC2C)
(attr virtual)
(fp_text reference TP101 (at 0 -1.998) (layer F.SilkS)
Schematic: Bugfixes, VU meter draft, first development PCB draft
2020-11-02 00:00:47 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(fp_text value Stage (at 0 2.05) (layer F.SilkS)
Schematic: Bugfixes, VU meter draft, first development PCB draft
2020-11-02 00:00:47 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(fp_circle (center 0 0) (end 1.5 0) (layer F.CrtYd) (width 0.05))
(fp_circle (center 0 0) (end 0 1.2) (layer F.SilkS) (width 0.12))
(fp_text user %R (at 0 -2) (layer F.Fab)
Move VU-Meter to own project
2020-11-09 00:52:43 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(pad 1 thru_hole circle (at 0 0) (size 2 2) (drill 1) (layers *.Cu *.Mask)
(net 41 /Monitor_Stage))
Move VU-Meter to own project
2020-11-09 00:52:43 +00:00
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(module Package_DIP:DIP-8_W7.62mm_Socket_LongPads (layer F.Cu) (tedit 5A02E8C5) (tstamp 5FA9E484)
(at 121.92 207.63 180)
(descr "8-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), Socket, LongPads")
(tags "THT DIP DIL PDIP 2.54mm 7.62mm 300mil Socket LongPads")
(path /5FB67AE3)
(fp_text reference U103 (at 3.81 -2.33) (layer F.SilkS)
Move VU-Meter to own project
2020-11-09 00:52:43 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(fp_text value LM386N-4 (at 3.81 9.95) (layer F.Fab)
Schematic: Bugfixes, VU meter draft, first development PCB draft
2020-11-02 00:00:47 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(fp_line (start 9.15 -1.6) (end -1.55 -1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start 9.15 9.2) (end 9.15 -1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.55 9.2) (end 9.15 9.2) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.55 -1.6) (end -1.55 9.2) (layer F.CrtYd) (width 0.05))
(fp_line (start 9.06 -1.39) (end -1.44 -1.39) (layer F.SilkS) (width 0.12))
(fp_line (start 9.06 9.01) (end 9.06 -1.39) (layer F.SilkS) (width 0.12))
(fp_line (start -1.44 9.01) (end 9.06 9.01) (layer F.SilkS) (width 0.12))
(fp_line (start -1.44 -1.39) (end -1.44 9.01) (layer F.SilkS) (width 0.12))
(fp_line (start 6.06 -1.33) (end 4.81 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 6.06 8.95) (end 6.06 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 1.56 8.95) (end 6.06 8.95) (layer F.SilkS) (width 0.12))
(fp_line (start 1.56 -1.33) (end 1.56 8.95) (layer F.SilkS) (width 0.12))
(fp_line (start 2.81 -1.33) (end 1.56 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 8.89 -1.33) (end -1.27 -1.33) (layer F.Fab) (width 0.1))
(fp_line (start 8.89 8.95) (end 8.89 -1.33) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 8.95) (end 8.89 8.95) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 -1.33) (end -1.27 8.95) (layer F.Fab) (width 0.1))
(fp_line (start 0.635 -0.27) (end 1.635 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start 0.635 8.89) (end 0.635 -0.27) (layer F.Fab) (width 0.1))
(fp_line (start 6.985 8.89) (end 0.635 8.89) (layer F.Fab) (width 0.1))
(fp_line (start 6.985 -1.27) (end 6.985 8.89) (layer F.Fab) (width 0.1))
(fp_line (start 1.635 -1.27) (end 6.985 -1.27) (layer F.Fab) (width 0.1))
(fp_text user %R (at 3.81 3.81) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_arc (start 3.81 -1.33) (end 2.81 -1.33) (angle -180) (layer F.SilkS) (width 0.12))
(pad 8 thru_hole oval (at 7.62 0 180) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask))
(pad 4 thru_hole oval (at 0 7.62 180) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 3 GND))
(pad 7 thru_hole oval (at 7.62 2.54 180) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 8 "Net-(C108-Pad1)"))
(pad 3 thru_hole oval (at 0 5.08 180) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 16 "Net-(C114-Pad2)"))
(pad 6 thru_hole oval (at 7.62 5.08 180) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 2 +15V))
(pad 2 thru_hole oval (at 0 2.54 180) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 3 GND))
(pad 5 thru_hole oval (at 7.62 7.62 180) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 11 "Net-(C110-Pad1)"))
(pad 1 thru_hole rect (at 0 0 180) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask))
(model ${KISYS3DMOD}/Package_DIP.3dshapes/DIP-8_W7.62mm_Socket.wrl
Schematic: Bugfixes, VU meter draft, first development PCB draft
2020-11-02 00:00:47 +00:00
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(module Resistor_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal (layer F.Cu) (tedit 5AE5139B) (tstamp 5FA9E19E)
(at 114.3 187.31 90)
Schematic: Bugfixes, VU meter draft, first development PCB draft
2020-11-02 00:00:47 +00:00
(descr "Resistor, Axial_DIN0207 series, Axial, Horizontal, pin pitch=10.16mm, 0.25W = 1/4W, length*diameter=6.3*2.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf")
(tags "Resistor Axial_DIN0207 series Axial Horizontal pin pitch 10.16mm 0.25W = 1/4W length 6.3mm diameter 2.5mm")
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(path /5FB6DC67)
(fp_text reference R116 (at 5.08 -2.37 90) (layer F.SilkS)
Schematic: Bugfixes, VU meter draft, first development PCB draft
2020-11-02 00:00:47 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(fp_text value 12R (at 5.08 2.37 90) (layer F.Fab)
Schematic: Bugfixes, VU meter draft, first development PCB draft
2020-11-02 00:00:47 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 11.21 -1.5) (end -1.05 -1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 11.21 1.5) (end 11.21 -1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.5) (end 11.21 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 -1.5) (end -1.05 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 9.12 0) (end 8.35 0) (layer F.SilkS) (width 0.12))
(fp_line (start 1.04 0) (end 1.81 0) (layer F.SilkS) (width 0.12))
(fp_line (start 8.35 -1.37) (end 1.81 -1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 8.35 1.37) (end 8.35 -1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 1.81 1.37) (end 8.35 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 1.81 -1.37) (end 1.81 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 10.16 0) (end 8.23 0) (layer F.Fab) (width 0.1))
(fp_line (start 0 0) (end 1.93 0) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 -1.25) (end 1.93 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 1.25) (end 8.23 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 1.93 1.25) (end 8.23 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 1.93 -1.25) (end 1.93 1.25) (layer F.Fab) (width 0.1))
final fixes for first prototype PCB order
2020-11-12 23:40:18 +00:00
(fp_text user %R (at 5.08 0 90) (layer F.Fab)
Schematic: Bugfixes, VU meter draft, first development PCB draft
2020-11-02 00:00:47 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(pad 2 thru_hole oval (at 10.16 0 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 3 GND))
(pad 1 thru_hole circle (at 0 0 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 13 "Net-(C112-Pad2)"))
Schematic: Bugfixes, VU meter draft, first development PCB draft
2020-11-02 00:00:47 +00:00
(model ${KISYS3DMOD}/Resistor_THT.3dshapes/R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(module Resistor_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal (layer F.Cu) (tedit 5AE5139B) (tstamp 5FA9E187)
(at 120.65 211.44 270)
Schematic: Bugfixes, VU meter draft, first development PCB draft
2020-11-02 00:00:47 +00:00
(descr "Resistor, Axial_DIN0207 series, Axial, Horizontal, pin pitch=10.16mm, 0.25W = 1/4W, length*diameter=6.3*2.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf")
(tags "Resistor Axial_DIN0207 series Axial Horizontal pin pitch 10.16mm 0.25W = 1/4W length 6.3mm diameter 2.5mm")
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(path /5FE4A41D)
(fp_text reference R113 (at 5.08 -2.37 90) (layer F.SilkS)
Schematic: Bugfixes, VU meter draft, first development PCB draft
2020-11-02 00:00:47 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(fp_text value 330K (at 5.08 2.37 90) (layer F.Fab)
Schematic: Bugfixes, VU meter draft, first development PCB draft
2020-11-02 00:00:47 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 11.21 -1.5) (end -1.05 -1.5) (layer F.CrtYd) (width 0.05))
Move VU-Meter to own project
2020-11-09 00:52:43 +00:00
(fp_line (start 11.21 1.5) (end 11.21 -1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.5) (end 11.21 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 -1.5) (end -1.05 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 9.12 0) (end 8.35 0) (layer F.SilkS) (width 0.12))
(fp_line (start 1.04 0) (end 1.81 0) (layer F.SilkS) (width 0.12))
(fp_line (start 8.35 -1.37) (end 1.81 -1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 8.35 1.37) (end 8.35 -1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 1.81 1.37) (end 8.35 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 1.81 -1.37) (end 1.81 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 10.16 0) (end 8.23 0) (layer F.Fab) (width 0.1))
(fp_line (start 0 0) (end 1.93 0) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 -1.25) (end 1.93 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 1.25) (end 8.23 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 1.93 1.25) (end 8.23 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 1.93 -1.25) (end 1.93 1.25) (layer F.Fab) (width 0.1))
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(fp_text user %R (at 5.08 0 90) (layer F.Fab)
Schematic: Bugfixes, VU meter draft, first development PCB draft
2020-11-02 00:00:47 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(pad 2 thru_hole oval (at 10.16 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 47 "Net-(R113-Pad2)"))
(pad 1 thru_hole circle (at 0 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 78 AmpIn))
Schematic: Bugfixes, VU meter draft, first development PCB draft
2020-11-02 00:00:47 +00:00
(model ${KISYS3DMOD}/Resistor_THT.3dshapes/R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(module Capacitor_THT:C_Disc_D5.0mm_W2.5mm_P5.00mm (layer F.Cu) (tedit 5AE50EF0) (tstamp 5FA9DBB8)
(at 114.3 194.93 90)
(descr "C, Disc series, Radial, pin pitch=5.00mm, , diameter*width=5*2.5mm^2, Capacitor, http://cdn-reichelt.de/documents/datenblatt/B300/DS_KERKO_TC.pdf")
(tags "C Disc series Radial pin pitch 5.00mm diameter 5mm width 2.5mm Capacitor")
(path /5FB69AC8)
(fp_text reference C112 (at 2.5 -2.5 90) (layer F.SilkS)
Schematic: Bugfixes, VU meter draft, first development PCB draft
2020-11-02 00:00:47 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(fp_text value 47nF (at 2.5 2.5 90) (layer F.Fab)
Schematic: Bugfixes, VU meter draft, first development PCB draft
2020-11-02 00:00:47 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(fp_line (start 6.05 -1.5) (end -1.05 -1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 6.05 1.5) (end 6.05 -1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.5) (end 6.05 1.5) (layer F.CrtYd) (width 0.05))
final fixes for first prototype PCB order
2020-11-12 23:40:18 +00:00
(fp_line (start -1.05 -1.5) (end -1.05 1.5) (layer F.CrtYd) (width 0.05))
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(fp_line (start 5.12 1.055) (end 5.12 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 5.12 -1.37) (end 5.12 -1.055) (layer F.SilkS) (width 0.12))
(fp_line (start -0.12 1.055) (end -0.12 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start -0.12 -1.37) (end -0.12 -1.055) (layer F.SilkS) (width 0.12))
(fp_line (start -0.12 1.37) (end 5.12 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start -0.12 -1.37) (end 5.12 -1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 5 -1.25) (end 0 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 5 1.25) (end 5 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 0 1.25) (end 5 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 0 -1.25) (end 0 1.25) (layer F.Fab) (width 0.1))
(fp_text user %R (at 2.5 0 90) (layer F.Fab)
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(pad 2 thru_hole circle (at 5 0 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 13 "Net-(C112-Pad2)"))
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
(pad 1 thru_hole circle (at 0 0 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(net 11 "Net-(C110-Pad1)"))
(model ${KISYS3DMOD}/Capacitor_THT.3dshapes/C_Disc_D5.0mm_W2.5mm_P5.00mm.wrl
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(module Capacitor_THT:C_Disc_D5.0mm_W2.5mm_P5.00mm (layer F.Cu) (tedit 5AE50EF0) (tstamp 5FA9D9E3)
(at 118.11 193.66)
(descr "C, Disc series, Radial, pin pitch=5.00mm, , diameter*width=5*2.5mm^2, Capacitor, http://cdn-reichelt.de/documents/datenblatt/B300/DS_KERKO_TC.pdf")
(tags "C Disc series Radial pin pitch 5.00mm diameter 5mm width 2.5mm Capacitor")
(path /5FF934F9)
(fp_text reference C105 (at 2.5 -2.5) (layer F.SilkS)
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(fp_text value 100nF (at 2.5 2.5) (layer F.Fab)
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(fp_line (start 6.05 -1.5) (end -1.05 -1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 6.05 1.5) (end 6.05 -1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.5) (end 6.05 1.5) (layer F.CrtYd) (width 0.05))
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
(fp_line (start -1.05 -1.5) (end -1.05 1.5) (layer F.CrtYd) (width 0.05))
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(fp_line (start 5.12 1.055) (end 5.12 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 5.12 -1.37) (end 5.12 -1.055) (layer F.SilkS) (width 0.12))
(fp_line (start -0.12 1.055) (end -0.12 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start -0.12 -1.37) (end -0.12 -1.055) (layer F.SilkS) (width 0.12))
(fp_line (start -0.12 1.37) (end 5.12 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start -0.12 -1.37) (end 5.12 -1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 5 -1.25) (end 0 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 5 1.25) (end 5 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 0 1.25) (end 5 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 0 -1.25) (end 0 1.25) (layer F.Fab) (width 0.1))
(fp_text user %R (at 2.5 0) (layer F.Fab)
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(pad 2 thru_hole circle (at 5 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 3 GND))
(pad 1 thru_hole circle (at 0 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 2 +15V))
(model ${KISYS3DMOD}/Capacitor_THT.3dshapes/C_Disc_D5.0mm_W2.5mm_P5.00mm.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Capacitor_THT:C_Disc_D5.0mm_W2.5mm_P5.00mm (layer F.Cu) (tedit 5AE50EF0) (tstamp 5F9FD558)
(at 97.79 205.09 180)
(descr "C, Disc series, Radial, pin pitch=5.00mm, , diameter*width=5*2.5mm^2, Capacitor, http://cdn-reichelt.de/documents/datenblatt/B300/DS_KERKO_TC.pdf")
(tags "C Disc series Radial pin pitch 5.00mm diameter 5mm width 2.5mm Capacitor")
(path /5F862FE2)
(fp_text reference C104 (at 2.5 -2.5) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 100nF (at 2.5 2.5) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 0 -1.25) (end 0 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 0 1.25) (end 5 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 5 1.25) (end 5 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 5 -1.25) (end 0 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start -0.12 -1.37) (end 5.12 -1.37) (layer F.SilkS) (width 0.12))
(fp_line (start -0.12 1.37) (end 5.12 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start -0.12 -1.37) (end -0.12 -1.055) (layer F.SilkS) (width 0.12))
(fp_line (start -0.12 1.055) (end -0.12 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 5.12 -1.37) (end 5.12 -1.055) (layer F.SilkS) (width 0.12))
(fp_line (start 5.12 1.055) (end 5.12 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start -1.05 -1.5) (end -1.05 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.5) (end 6.05 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 6.05 1.5) (end 6.05 -1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 6.05 -1.5) (end -1.05 -1.5) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 2.5 0) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 2 thru_hole circle (at 5 0 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 1 -15V))
(pad 1 thru_hole circle (at 0 0 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 3 GND))
(model ${KISYS3DMOD}/Capacitor_THT.3dshapes/C_Disc_D5.0mm_W2.5mm_P5.00mm.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Capacitor_THT:C_Disc_D5.0mm_W2.5mm_P5.00mm (layer B.Cu) (tedit 5AE50EF0) (tstamp 5F9FD582)
(at 73.66 125.65 90)
(descr "C, Disc series, Radial, pin pitch=5.00mm, , diameter*width=5*2.5mm^2, Capacitor, http://cdn-reichelt.de/documents/datenblatt/B300/DS_KERKO_TC.pdf")
(tags "C Disc series Radial pin pitch 5.00mm diameter 5mm width 2.5mm Capacitor")
(path /5FFAA88C)
(fp_text reference C116 (at 2.5 2.5 270) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value 100nF (at 2.5 -2.5 270) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_line (start 0 1.25) (end 0 -1.25) (layer B.Fab) (width 0.1))
(fp_line (start 0 -1.25) (end 5 -1.25) (layer B.Fab) (width 0.1))
(fp_line (start 5 -1.25) (end 5 1.25) (layer B.Fab) (width 0.1))
(fp_line (start 5 1.25) (end 0 1.25) (layer B.Fab) (width 0.1))
(fp_line (start -0.12 1.37) (end 5.12 1.37) (layer B.SilkS) (width 0.12))
(fp_line (start -0.12 -1.37) (end 5.12 -1.37) (layer B.SilkS) (width 0.12))
(fp_line (start -0.12 1.37) (end -0.12 1.055) (layer B.SilkS) (width 0.12))
(fp_line (start -0.12 -1.055) (end -0.12 -1.37) (layer B.SilkS) (width 0.12))
(fp_line (start 5.12 1.37) (end 5.12 1.055) (layer B.SilkS) (width 0.12))
(fp_line (start 5.12 -1.055) (end 5.12 -1.37) (layer B.SilkS) (width 0.12))
(fp_line (start -1.05 1.5) (end -1.05 -1.5) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.05 -1.5) (end 6.05 -1.5) (layer B.CrtYd) (width 0.05))
(fp_line (start 6.05 -1.5) (end 6.05 1.5) (layer B.CrtYd) (width 0.05))
(fp_line (start 6.05 1.5) (end -1.05 1.5) (layer B.CrtYd) (width 0.05))
(fp_text user %R (at 2.5 0 270) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(pad 2 thru_hole circle (at 5 0 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 1 -15V))
(pad 1 thru_hole circle (at 0 0 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 3 GND))
(model ${KISYS3DMOD}/Capacitor_THT.3dshapes/C_Disc_D5.0mm_W2.5mm_P5.00mm.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Capacitor_THT:C_Disc_D5.0mm_W2.5mm_P5.00mm (layer B.Cu) (tedit 5AE50EF0) (tstamp 5F9FD597)
(at 55.88 120.65 270)
(descr "C, Disc series, Radial, pin pitch=5.00mm, , diameter*width=5*2.5mm^2, Capacitor, http://cdn-reichelt.de/documents/datenblatt/B300/DS_KERKO_TC.pdf")
(tags "C Disc series Radial pin pitch 5.00mm diameter 5mm width 2.5mm Capacitor")
(path /5FFAA892)
(fp_text reference C117 (at 2.5 2.5 270) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value 100nF (at 2.5 -2.5 270) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_line (start 6.05 1.5) (end -1.05 1.5) (layer B.CrtYd) (width 0.05))
(fp_line (start 6.05 -1.5) (end 6.05 1.5) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.05 -1.5) (end 6.05 -1.5) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.05 1.5) (end -1.05 -1.5) (layer B.CrtYd) (width 0.05))
(fp_line (start 5.12 -1.055) (end 5.12 -1.37) (layer B.SilkS) (width 0.12))
(fp_line (start 5.12 1.37) (end 5.12 1.055) (layer B.SilkS) (width 0.12))
(fp_line (start -0.12 -1.055) (end -0.12 -1.37) (layer B.SilkS) (width 0.12))
(fp_line (start -0.12 1.37) (end -0.12 1.055) (layer B.SilkS) (width 0.12))
(fp_line (start -0.12 -1.37) (end 5.12 -1.37) (layer B.SilkS) (width 0.12))
(fp_line (start -0.12 1.37) (end 5.12 1.37) (layer B.SilkS) (width 0.12))
(fp_line (start 5 1.25) (end 0 1.25) (layer B.Fab) (width 0.1))
(fp_line (start 5 -1.25) (end 5 1.25) (layer B.Fab) (width 0.1))
(fp_line (start 0 -1.25) (end 5 -1.25) (layer B.Fab) (width 0.1))
(fp_line (start 0 1.25) (end 0 -1.25) (layer B.Fab) (width 0.1))
(fp_text user %R (at 2.5 0 270) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
(pad 1 thru_hole circle (at 0 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(net 3 GND))
(pad 2 thru_hole circle (at 5 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 2 +15V))
(model ${KISYS3DMOD}/Capacitor_THT.3dshapes/C_Disc_D5.0mm_W2.5mm_P5.00mm.wrl
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(module Capacitor_THT:C_Disc_D5.0mm_W2.5mm_P5.00mm (layer F.Cu) (tedit 5AE50EF0) (tstamp 5F9FD68D)
(at 92.71 177.15)
(descr "C, Disc series, Radial, pin pitch=5.00mm, , diameter*width=5*2.5mm^2, Capacitor, http://cdn-reichelt.de/documents/datenblatt/B300/DS_KERKO_TC.pdf")
(tags "C Disc series Radial pin pitch 5.00mm diameter 5mm width 2.5mm Capacitor")
(path /5F8504A1)
(fp_text reference C115 (at 2.5 -2.5) (layer F.SilkS)
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(fp_text value 100nF (at 2.5 2.5) (layer F.Fab)
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(fp_line (start 6.05 -1.5) (end -1.05 -1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 6.05 1.5) (end 6.05 -1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.5) (end 6.05 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 -1.5) (end -1.05 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 5.12 1.055) (end 5.12 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 5.12 -1.37) (end 5.12 -1.055) (layer F.SilkS) (width 0.12))
(fp_line (start -0.12 1.055) (end -0.12 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start -0.12 -1.37) (end -0.12 -1.055) (layer F.SilkS) (width 0.12))
(fp_line (start -0.12 1.37) (end 5.12 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start -0.12 -1.37) (end 5.12 -1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 5 -1.25) (end 0 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 5 1.25) (end 5 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 0 1.25) (end 5 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 0 -1.25) (end 0 1.25) (layer F.Fab) (width 0.1))
(fp_text user %R (at 2.5 0) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 1 thru_hole circle (at 0 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 2 +15V))
(pad 2 thru_hole circle (at 5 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 3 GND))
(model ${KISYS3DMOD}/Capacitor_THT.3dshapes/C_Disc_D5.0mm_W2.5mm_P5.00mm.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Capacitor_THT:C_Disc_D5.0mm_W2.5mm_P5.00mm (layer F.Cu) (tedit 5AE50EF0) (tstamp 5F9FD921)
(at 66.04 97.79 270)
(descr "C, Disc series, Radial, pin pitch=5.00mm, , diameter*width=5*2.5mm^2, Capacitor, http://cdn-reichelt.de/documents/datenblatt/B300/DS_KERKO_TC.pdf")
(tags "C Disc series Radial pin pitch 5.00mm diameter 5mm width 2.5mm Capacitor")
(path /60AA92C3)
(fp_text reference C106 (at 2.5 -2.54 90) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 100nF (at 2.5 2.5 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 6.05 -1.5) (end -1.05 -1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 6.05 1.5) (end 6.05 -1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.5) (end 6.05 1.5) (layer F.CrtYd) (width 0.05))
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
(fp_line (start -1.05 -1.5) (end -1.05 1.5) (layer F.CrtYd) (width 0.05))
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(fp_line (start 5.12 1.055) (end 5.12 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 5.12 -1.37) (end 5.12 -1.055) (layer F.SilkS) (width 0.12))
(fp_line (start -0.12 1.055) (end -0.12 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start -0.12 -1.37) (end -0.12 -1.055) (layer F.SilkS) (width 0.12))
(fp_line (start -0.12 1.37) (end 5.12 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start -0.12 -1.37) (end 5.12 -1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 5 -1.25) (end 0 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 5 1.25) (end 5 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 0 1.25) (end 5 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 0 -1.25) (end 0 1.25) (layer F.Fab) (width 0.1))
(fp_text user %R (at 2.5 0 90) (layer F.Fab)
Schematic: Bugfixes, VU meter draft, first development PCB draft
2020-11-02 00:00:47 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(pad 1 thru_hole circle (at 0 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 75 /PreampOut))
(pad 2 thru_hole circle (at 5 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 5 "Net-(C106-Pad2)"))
(model ${KISYS3DMOD}/Capacitor_THT.3dshapes/C_Disc_D5.0mm_W2.5mm_P5.00mm.wrl
Schematic: Bugfixes, VU meter draft, first development PCB draft
2020-11-02 00:00:47 +00:00
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(module Resistor_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal (layer F.Cu) (tedit 5AE5139B) (tstamp 5F9FDCD0)
(at 80.01 188.58 180)
final fixes for first prototype PCB order
2020-11-12 23:40:18 +00:00
(descr "Resistor, Axial_DIN0207 series, Axial, Horizontal, pin pitch=10.16mm, 0.25W = 1/4W, length*diameter=6.3*2.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf")
(tags "Resistor Axial_DIN0207 series Axial Horizontal pin pitch 10.16mm 0.25W = 1/4W length 6.3mm diameter 2.5mm")
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(path /5F83A5E0)
(fp_text reference R103 (at 5.08 -2.37) (layer F.SilkS)
Schematic: Bugfixes, VU meter draft, first development PCB draft
2020-11-02 00:00:47 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(fp_text value "1K 1%" (at 5.08 2.37) (layer F.Fab)
Schematic: Bugfixes, VU meter draft, first development PCB draft
2020-11-02 00:00:47 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
final fixes for first prototype PCB order
2020-11-12 23:40:18 +00:00
(fp_line (start 1.93 -1.25) (end 1.93 1.25) (layer F.Fab) (width 0.1))
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
(fp_line (start 1.93 1.25) (end 8.23 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 1.25) (end 8.23 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 -1.25) (end 1.93 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 0 0) (end 1.93 0) (layer F.Fab) (width 0.1))
(fp_line (start 10.16 0) (end 8.23 0) (layer F.Fab) (width 0.1))
(fp_line (start 1.81 -1.37) (end 1.81 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 1.81 1.37) (end 8.35 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 8.35 1.37) (end 8.35 -1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 8.35 -1.37) (end 1.81 -1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 1.04 0) (end 1.81 0) (layer F.SilkS) (width 0.12))
(fp_line (start 9.12 0) (end 8.35 0) (layer F.SilkS) (width 0.12))
(fp_line (start -1.05 -1.5) (end -1.05 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.5) (end 11.21 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 11.21 1.5) (end 11.21 -1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 11.21 -1.5) (end -1.05 -1.5) (layer F.CrtYd) (width 0.05))
final fixes for first prototype PCB order
2020-11-12 23:40:18 +00:00
(fp_text user %R (at 5.08 0) (layer F.Fab)
Schematic: Bugfixes, VU meter draft, first development PCB draft
2020-11-02 00:00:47 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
final fixes for first prototype PCB order
2020-11-12 23:40:18 +00:00
(pad 2 thru_hole oval (at 10.16 0 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(net 6 "Net-(C107-Pad2)"))
final fixes for first prototype PCB order
2020-11-12 23:40:18 +00:00
(pad 1 thru_hole circle (at 0 0 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(net 43 "Net-(R103-Pad1)"))
final fixes for first prototype PCB order
2020-11-12 23:40:18 +00:00
(model ${KISYS3DMOD}/Resistor_THT.3dshapes/R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal.wrl
Schematic: Bugfixes, VU meter draft, first development PCB draft
2020-11-02 00:00:47 +00:00
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(module Resistor_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal (layer F.Cu) (tedit 5AE5139B) (tstamp 5F9FDCE7)
(at 87.63 182.23)
final fixes for first prototype PCB order
2020-11-12 23:40:18 +00:00
(descr "Resistor, Axial_DIN0207 series, Axial, Horizontal, pin pitch=10.16mm, 0.25W = 1/4W, length*diameter=6.3*2.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf")
(tags "Resistor Axial_DIN0207 series Axial Horizontal pin pitch 10.16mm 0.25W = 1/4W length 6.3mm diameter 2.5mm")
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(path /5F84960A)
(fp_text reference R104 (at 5.08 -2.37) (layer F.SilkS)
Schematic: Bugfixes, VU meter draft, first development PCB draft
2020-11-02 00:00:47 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(fp_text value "330K 1%" (at 5.08 2.37) (layer F.Fab)
Schematic: Bugfixes, VU meter draft, first development PCB draft
2020-11-02 00:00:47 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
final fixes for first prototype PCB order
2020-11-12 23:40:18 +00:00
(fp_line (start 1.93 -1.25) (end 1.93 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 1.93 1.25) (end 8.23 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 1.25) (end 8.23 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 -1.25) (end 1.93 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 0 0) (end 1.93 0) (layer F.Fab) (width 0.1))
(fp_line (start 10.16 0) (end 8.23 0) (layer F.Fab) (width 0.1))
(fp_line (start 1.81 -1.37) (end 1.81 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 1.81 1.37) (end 8.35 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 8.35 1.37) (end 8.35 -1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 8.35 -1.37) (end 1.81 -1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 1.04 0) (end 1.81 0) (layer F.SilkS) (width 0.12))
(fp_line (start 9.12 0) (end 8.35 0) (layer F.SilkS) (width 0.12))
(fp_line (start -1.05 -1.5) (end -1.05 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.5) (end 11.21 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 11.21 1.5) (end 11.21 -1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 11.21 -1.5) (end -1.05 -1.5) (layer F.CrtYd) (width 0.05))
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
(fp_text user %R (at 5.08 0) (layer F.Fab)
Schematic: Bugfixes, VU meter draft, first development PCB draft
2020-11-02 00:00:47 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(pad 2 thru_hole oval (at 10.16 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 9 "Net-(C109-Pad1)"))
(pad 1 thru_hole circle (at 0 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 43 "Net-(R103-Pad1)"))
final fixes for first prototype PCB order
2020-11-12 23:40:18 +00:00
(model ${KISYS3DMOD}/Resistor_THT.3dshapes/R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal.wrl
Schematic: Bugfixes, VU meter draft, first development PCB draft
2020-11-02 00:00:47 +00:00
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(module Resistor_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal (layer F.Cu) (tedit 5AE5139B) (tstamp 5F9FDD46)
(at 83.82 187.31 270)
final fixes for first prototype PCB order
2020-11-12 23:40:18 +00:00
(descr "Resistor, Axial_DIN0207 series, Axial, Horizontal, pin pitch=10.16mm, 0.25W = 1/4W, length*diameter=6.3*2.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf")
(tags "Resistor Axial_DIN0207 series Axial Horizontal pin pitch 10.16mm 0.25W = 1/4W length 6.3mm diameter 2.5mm")
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(path /5F83F337)
(fp_text reference R109 (at 5.08 -2.37 90) (layer F.SilkS)
Schematic: Bugfixes, VU meter draft, first development PCB draft
2020-11-02 00:00:47 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(fp_text value "27K 1%" (at 5.08 2.37 90) (layer F.Fab)
Schematic: Bugfixes, VU meter draft, first development PCB draft
2020-11-02 00:00:47 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
final fixes for first prototype PCB order
2020-11-12 23:40:18 +00:00
(fp_line (start 11.21 -1.5) (end -1.05 -1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 11.21 1.5) (end 11.21 -1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.5) (end 11.21 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 -1.5) (end -1.05 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 9.12 0) (end 8.35 0) (layer F.SilkS) (width 0.12))
(fp_line (start 1.04 0) (end 1.81 0) (layer F.SilkS) (width 0.12))
(fp_line (start 8.35 -1.37) (end 1.81 -1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 8.35 1.37) (end 8.35 -1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 1.81 1.37) (end 8.35 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 1.81 -1.37) (end 1.81 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 10.16 0) (end 8.23 0) (layer F.Fab) (width 0.1))
(fp_line (start 0 0) (end 1.93 0) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 -1.25) (end 1.93 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 1.25) (end 8.23 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 1.93 1.25) (end 8.23 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 1.93 -1.25) (end 1.93 1.25) (layer F.Fab) (width 0.1))
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
(fp_text user %R (at 5.08 0 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 1 thru_hole circle (at 0 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(net 43 "Net-(R103-Pad1)"))
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
(pad 2 thru_hole oval (at 10.16 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(net 46 "Net-(R109-Pad2)"))
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
(model ${KISYS3DMOD}/Resistor_THT.3dshapes/R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(module Resistor_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal (layer F.Cu) (tedit 5AE5139B) (tstamp 5F9FDD5D)
(at 66.04 114.3 180)
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
(descr "Resistor, Axial_DIN0207 series, Axial, Horizontal, pin pitch=10.16mm, 0.25W = 1/4W, length*diameter=6.3*2.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf")
(tags "Resistor Axial_DIN0207 series Axial Horizontal pin pitch 10.16mm 0.25W = 1/4W length 6.3mm diameter 2.5mm")
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(path /5F83C638)
(fp_text reference R110 (at 5.08 -2.37) (layer F.SilkS)
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(fp_text value 330R (at 5.08 2.37) (layer F.Fab)
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 11.21 -1.5) (end -1.05 -1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 11.21 1.5) (end 11.21 -1.5) (layer F.CrtYd) (width 0.05))
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(fp_line (start -1.05 1.5) (end 11.21 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 -1.5) (end -1.05 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 9.12 0) (end 8.35 0) (layer F.SilkS) (width 0.12))
(fp_line (start 1.04 0) (end 1.81 0) (layer F.SilkS) (width 0.12))
(fp_line (start 8.35 -1.37) (end 1.81 -1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 8.35 1.37) (end 8.35 -1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 1.81 1.37) (end 8.35 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 1.81 -1.37) (end 1.81 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 10.16 0) (end 8.23 0) (layer F.Fab) (width 0.1))
(fp_line (start 0 0) (end 1.93 0) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 -1.25) (end 1.93 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 1.25) (end 8.23 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 1.93 1.25) (end 8.23 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 1.93 -1.25) (end 1.93 1.25) (layer F.Fab) (width 0.1))
final fixes for first prototype PCB order
2020-11-12 23:40:18 +00:00
(fp_text user %R (at 5.08 0) (layer F.Fab)
Move VU-Meter to own project
2020-11-09 00:52:43 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
final fixes for first prototype PCB order
2020-11-12 23:40:18 +00:00
(pad 1 thru_hole circle (at 0 0 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(net 5 "Net-(C106-Pad2)"))
(pad 2 thru_hole oval (at 10.16 0 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 79 MicGainIn))
final fixes for first prototype PCB order
2020-11-12 23:40:18 +00:00
(model ${KISYS3DMOD}/Resistor_THT.3dshapes/R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal.wrl
Schematic: Bugfixes, VU meter draft, first development PCB draft
2020-11-02 00:00:47 +00:00
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(module Resistor_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal (layer F.Cu) (tedit 5AE5139B) (tstamp 5F9FDD74)
(at 109.22 197.47 90)
final fixes for first prototype PCB order
2020-11-12 23:40:18 +00:00
(descr "Resistor, Axial_DIN0207 series, Axial, Horizontal, pin pitch=10.16mm, 0.25W = 1/4W, length*diameter=6.3*2.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf")
(tags "Resistor Axial_DIN0207 series Axial Horizontal pin pitch 10.16mm 0.25W = 1/4W length 6.3mm diameter 2.5mm")
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(path /5F86655E)
(fp_text reference R112 (at 5.08 -2.37 90) (layer F.SilkS)
Schematic: Bugfixes, VU meter draft, first development PCB draft
2020-11-02 00:00:47 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(fp_text value 820R (at 5.08 2.37 90) (layer F.Fab)
Schematic: Bugfixes, VU meter draft, first development PCB draft
2020-11-02 00:00:47 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
(fp_line (start 11.21 -1.5) (end -1.05 -1.5) (layer F.CrtYd) (width 0.05))
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(fp_line (start 11.21 1.5) (end 11.21 -1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.5) (end 11.21 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 -1.5) (end -1.05 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 9.12 0) (end 8.35 0) (layer F.SilkS) (width 0.12))
(fp_line (start 1.04 0) (end 1.81 0) (layer F.SilkS) (width 0.12))
(fp_line (start 8.35 -1.37) (end 1.81 -1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 8.35 1.37) (end 8.35 -1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 1.81 1.37) (end 8.35 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 1.81 -1.37) (end 1.81 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 10.16 0) (end 8.23 0) (layer F.Fab) (width 0.1))
(fp_line (start 0 0) (end 1.93 0) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 -1.25) (end 1.93 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 1.25) (end 8.23 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 1.93 1.25) (end 8.23 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 1.93 -1.25) (end 1.93 1.25) (layer F.Fab) (width 0.1))
final fixes for first prototype PCB order
2020-11-12 23:40:18 +00:00
(fp_text user %R (at 5.08 0 90) (layer F.Fab)
Schematic: Bugfixes, VU meter draft, first development PCB draft
2020-11-02 00:00:47 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(pad 1 thru_hole circle (at 0 0 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 77 MicPreOut))
(pad 2 thru_hole oval (at 10.16 0 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 3 GND))
final fixes for first prototype PCB order
2020-11-12 23:40:18 +00:00
(model ${KISYS3DMOD}/Resistor_THT.3dshapes/R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal.wrl
Schematic: Bugfixes, VU meter draft, first development PCB draft
2020-11-02 00:00:47 +00:00
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(module Resistor_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal (layer F.Cu) (tedit 5AE5139B) (tstamp 5F9FDDA2)
(at 64.77 130.81)
final fixes for first prototype PCB order
2020-11-12 23:40:18 +00:00
(descr "Resistor, Axial_DIN0207 series, Axial, Horizontal, pin pitch=10.16mm, 0.25W = 1/4W, length*diameter=6.3*2.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf")
(tags "Resistor Axial_DIN0207 series Axial Horizontal pin pitch 10.16mm 0.25W = 1/4W length 6.3mm diameter 2.5mm")
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(path /5FFF6743)
(fp_text reference R102 (at 7.62 -2.37) (layer F.SilkS)
Schematic: Bugfixes, VU meter draft, first development PCB draft
2020-11-02 00:00:47 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(fp_text value 22K (at 5.08 2.37) (layer F.Fab)
Schematic: Bugfixes, VU meter draft, first development PCB draft
2020-11-02 00:00:47 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
final fixes for first prototype PCB order
2020-11-12 23:40:18 +00:00
(fp_line (start 1.93 -1.25) (end 1.93 1.25) (layer F.Fab) (width 0.1))
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
(fp_line (start 1.93 1.25) (end 8.23 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 1.25) (end 8.23 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 -1.25) (end 1.93 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 0 0) (end 1.93 0) (layer F.Fab) (width 0.1))
(fp_line (start 10.16 0) (end 8.23 0) (layer F.Fab) (width 0.1))
(fp_line (start 1.81 -1.37) (end 1.81 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 1.81 1.37) (end 8.35 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 8.35 1.37) (end 8.35 -1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 8.35 -1.37) (end 1.81 -1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 1.04 0) (end 1.81 0) (layer F.SilkS) (width 0.12))
(fp_line (start 9.12 0) (end 8.35 0) (layer F.SilkS) (width 0.12))
(fp_line (start -1.05 -1.5) (end -1.05 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.5) (end 11.21 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 11.21 1.5) (end 11.21 -1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 11.21 -1.5) (end -1.05 -1.5) (layer F.CrtYd) (width 0.05))
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(fp_text user %R (at 5.08 0) (layer F.Fab)
final fixes for first prototype PCB order
2020-11-12 23:40:18 +00:00
(effects (font (size 1 1) (thickness 0.15)))
Schematic: Bugfixes, VU meter draft, first development PCB draft
2020-11-02 00:00:47 +00:00
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(pad 2 thru_hole oval (at 10.16 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 4 "Net-(C103-Pad2)"))
(pad 1 thru_hole circle (at 0 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 76 SumOut))
final fixes for first prototype PCB order
2020-11-12 23:40:18 +00:00
(model ${KISYS3DMOD}/Resistor_THT.3dshapes/R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal.wrl
Schematic: Bugfixes, VU meter draft, first development PCB draft
2020-11-02 00:00:47 +00:00
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(module Resistor_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal (layer F.Cu) (tedit 5AE5139B) (tstamp 5F9FDDB9)
(at 80.01 196.2 180)
final fixes for first prototype PCB order
2020-11-12 23:40:18 +00:00
(descr "Resistor, Axial_DIN0207 series, Axial, Horizontal, pin pitch=10.16mm, 0.25W = 1/4W, length*diameter=6.3*2.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf")
(tags "Resistor Axial_DIN0207 series Axial Horizontal pin pitch 10.16mm 0.25W = 1/4W length 6.3mm diameter 2.5mm")
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(path /5F84095A)
(fp_text reference R114 (at 5.08 -2.37) (layer F.SilkS)
Schematic: Bugfixes, VU meter draft, first development PCB draft
2020-11-02 00:00:47 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(fp_text value "1K 1%" (at 5.08 2.37) (layer F.Fab)
Schematic: Bugfixes, VU meter draft, first development PCB draft
2020-11-02 00:00:47 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
final fixes for first prototype PCB order
2020-11-12 23:40:18 +00:00
(fp_line (start 1.93 -1.25) (end 1.93 1.25) (layer F.Fab) (width 0.1))
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
(fp_line (start 1.93 1.25) (end 8.23 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 1.25) (end 8.23 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 -1.25) (end 1.93 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 0 0) (end 1.93 0) (layer F.Fab) (width 0.1))
(fp_line (start 10.16 0) (end 8.23 0) (layer F.Fab) (width 0.1))
(fp_line (start 1.81 -1.37) (end 1.81 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 1.81 1.37) (end 8.35 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 8.35 1.37) (end 8.35 -1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 8.35 -1.37) (end 1.81 -1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 1.04 0) (end 1.81 0) (layer F.SilkS) (width 0.12))
(fp_line (start 9.12 0) (end 8.35 0) (layer F.SilkS) (width 0.12))
(fp_line (start -1.05 -1.5) (end -1.05 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.5) (end 11.21 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 11.21 1.5) (end 11.21 -1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 11.21 -1.5) (end -1.05 -1.5) (layer F.CrtYd) (width 0.05))
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(fp_text user %R (at 5.08 0) (layer F.Fab)
Schematic: Bugfixes, VU meter draft, first development PCB draft
2020-11-02 00:00:47 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(pad 2 thru_hole oval (at 10.16 0 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 14 "Net-(C113-Pad2)"))
(pad 1 thru_hole circle (at 0 0 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 46 "Net-(R109-Pad2)"))
final fixes for first prototype PCB order
2020-11-12 23:40:18 +00:00
(model ${KISYS3DMOD}/Resistor_THT.3dshapes/R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
Refine headphone mix requirements, fix signal flow
2020-11-12 00:11:14 +00:00
)
final fixes for first prototype PCB order
2020-11-12 23:40:18 +00:00
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(module Resistor_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal (layer F.Cu) (tedit 5AE5139B) (tstamp 5F9FDDD0)
(at 97.79 200.01 180)
final fixes for first prototype PCB order
2020-11-12 23:40:18 +00:00
(descr "Resistor, Axial_DIN0207 series, Axial, Horizontal, pin pitch=10.16mm, 0.25W = 1/4W, length*diameter=6.3*2.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf")
(tags "Resistor Axial_DIN0207 series Axial Horizontal pin pitch 10.16mm 0.25W = 1/4W length 6.3mm diameter 2.5mm")
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(path /5F83D91E)
(fp_text reference R115 (at 5.08 -2.37) (layer F.SilkS)
final fixes for first prototype PCB order
2020-11-12 23:40:18 +00:00
(effects (font (size 1 1) (thickness 0.15)))
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
)
(fp_text value "330K 1%" (at 5.08 2.37) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
(fp_line (start 1.93 -1.25) (end 1.93 1.25) (layer F.Fab) (width 0.1))
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(fp_line (start 1.93 1.25) (end 8.23 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 1.25) (end 8.23 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 -1.25) (end 1.93 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 0 0) (end 1.93 0) (layer F.Fab) (width 0.1))
(fp_line (start 10.16 0) (end 8.23 0) (layer F.Fab) (width 0.1))
(fp_line (start 1.81 -1.37) (end 1.81 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 1.81 1.37) (end 8.35 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 8.35 1.37) (end 8.35 -1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 8.35 -1.37) (end 1.81 -1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 1.04 0) (end 1.81 0) (layer F.SilkS) (width 0.12))
(fp_line (start 9.12 0) (end 8.35 0) (layer F.SilkS) (width 0.12))
(fp_line (start -1.05 -1.5) (end -1.05 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.5) (end 11.21 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 11.21 1.5) (end 11.21 -1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 11.21 -1.5) (end -1.05 -1.5) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 5.08 0) (layer F.Fab)
final fixes for first prototype PCB order
2020-11-12 23:40:18 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(pad 2 thru_hole oval (at 10.16 0 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 46 "Net-(R109-Pad2)"))
(pad 1 thru_hole circle (at 0 0 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 3 GND))
final fixes for first prototype PCB order
2020-11-12 23:40:18 +00:00
(model ${KISYS3DMOD}/Resistor_THT.3dshapes/R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
Schematic: Bugfixes, VU meter draft, first development PCB draft
2020-11-02 00:00:47 +00:00
)
final fixes for first prototype PCB order
2020-11-12 23:40:18 +00:00
(module Resistor_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal (layer F.Cu) (tedit 5AE5139B) (tstamp 5F9FDEFB)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(at 72.39 95.25 270)
final fixes for first prototype PCB order
2020-11-12 23:40:18 +00:00
(descr "Resistor, Axial_DIN0207 series, Axial, Horizontal, pin pitch=10.16mm, 0.25W = 1/4W, length*diameter=6.3*2.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf")
(tags "Resistor Axial_DIN0207 series Axial Horizontal pin pitch 10.16mm 0.25W = 1/4W length 6.3mm diameter 2.5mm")
(path /60AAAB08)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(fp_text reference R105 (at 5.08 -2.37 90) (layer F.SilkS)
final fixes for first prototype PCB order
2020-11-12 23:40:18 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(fp_text value 56R (at 5.08 2.37 90) (layer F.Fab)
final fixes for first prototype PCB order
2020-11-12 23:40:18 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 11.21 -1.5) (end -1.05 -1.5) (layer F.CrtYd) (width 0.05))
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
(fp_line (start 11.21 1.5) (end 11.21 -1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.5) (end 11.21 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 -1.5) (end -1.05 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 9.12 0) (end 8.35 0) (layer F.SilkS) (width 0.12))
(fp_line (start 1.04 0) (end 1.81 0) (layer F.SilkS) (width 0.12))
(fp_line (start 8.35 -1.37) (end 1.81 -1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 8.35 1.37) (end 8.35 -1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 1.81 1.37) (end 8.35 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 1.81 -1.37) (end 1.81 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 10.16 0) (end 8.23 0) (layer F.Fab) (width 0.1))
(fp_line (start 0 0) (end 1.93 0) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 -1.25) (end 1.93 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 1.25) (end 8.23 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 1.93 1.25) (end 8.23 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 1.93 -1.25) (end 1.93 1.25) (layer F.Fab) (width 0.1))
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(fp_text user %R (at 5.08 0 90) (layer F.Fab)
final fixes for first prototype PCB order
2020-11-12 23:40:18 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(pad 1 thru_hole circle (at 0 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 44 "Net-(R105-Pad1)"))
(pad 2 thru_hole oval (at 10.16 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 5 "Net-(C106-Pad2)"))
final fixes for first prototype PCB order
2020-11-12 23:40:18 +00:00
(model ${KISYS3DMOD}/Resistor_THT.3dshapes/R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
Schematic: Bugfixes, VU meter draft, first development PCB draft
2020-11-02 00:00:47 +00:00
)
final fixes for first prototype PCB order
2020-11-12 23:40:18 +00:00
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
(module Package_DIP:DIP-8_W7.62mm_Socket_LongPads (layer F.Cu) (tedit 5A02E8C5) (tstamp 5F9FE24A)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(at 88.9 187.31)
final fixes for first prototype PCB order
2020-11-12 23:40:18 +00:00
(descr "8-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), Socket, LongPads")
(tags "THT DIP DIL PDIP 2.54mm 7.62mm 300mil Socket LongPads")
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
(path /5F80D909)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(fp_text reference U101 (at 3.81 -2.33) (layer F.SilkS)
final fixes for first prototype PCB order
2020-11-12 23:40:18 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
(fp_text value NE5534 (at 3.81 9.95) (layer F.Fab)
final fixes for first prototype PCB order
2020-11-12 23:40:18 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 9.15 -1.6) (end -1.55 -1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start 9.15 9.2) (end 9.15 -1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.55 9.2) (end 9.15 9.2) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.55 -1.6) (end -1.55 9.2) (layer F.CrtYd) (width 0.05))
(fp_line (start 9.06 -1.39) (end -1.44 -1.39) (layer F.SilkS) (width 0.12))
(fp_line (start 9.06 9.01) (end 9.06 -1.39) (layer F.SilkS) (width 0.12))
(fp_line (start -1.44 9.01) (end 9.06 9.01) (layer F.SilkS) (width 0.12))
(fp_line (start -1.44 -1.39) (end -1.44 9.01) (layer F.SilkS) (width 0.12))
(fp_line (start 6.06 -1.33) (end 4.81 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 6.06 8.95) (end 6.06 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 1.56 8.95) (end 6.06 8.95) (layer F.SilkS) (width 0.12))
(fp_line (start 1.56 -1.33) (end 1.56 8.95) (layer F.SilkS) (width 0.12))
(fp_line (start 2.81 -1.33) (end 1.56 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 8.89 -1.33) (end -1.27 -1.33) (layer F.Fab) (width 0.1))
(fp_line (start 8.89 8.95) (end 8.89 -1.33) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 8.95) (end 8.89 8.95) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 -1.33) (end -1.27 8.95) (layer F.Fab) (width 0.1))
(fp_line (start 0.635 -0.27) (end 1.635 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start 0.635 8.89) (end 0.635 -0.27) (layer F.Fab) (width 0.1))
(fp_line (start 6.985 8.89) (end 0.635 8.89) (layer F.Fab) (width 0.1))
(fp_line (start 6.985 -1.27) (end 6.985 8.89) (layer F.Fab) (width 0.1))
(fp_line (start 1.635 -1.27) (end 6.985 -1.27) (layer F.Fab) (width 0.1))
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
(fp_arc (start 3.81 -1.33) (end 2.81 -1.33) (angle -180) (layer F.SilkS) (width 0.12))
final fixes for first prototype PCB order
2020-11-12 23:40:18 +00:00
(fp_text user %R (at 3.81 3.81) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
(pad 1 thru_hole rect (at 0 0) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask))
(pad 5 thru_hole oval (at 7.62 7.62) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask))
final fixes for first prototype PCB order
2020-11-12 23:40:18 +00:00
(pad 2 thru_hole oval (at 0 2.54) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(net 43 "Net-(R103-Pad1)"))
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
(pad 6 thru_hole oval (at 7.62 5.08) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(net 9 "Net-(C109-Pad1)"))
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
(pad 3 thru_hole oval (at 0 5.08) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(net 46 "Net-(R109-Pad2)"))
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
(pad 7 thru_hole oval (at 7.62 2.54) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(net 2 +15V))
Main: Add 15V phantom power
2020-12-13 23:31:43 +00:00
(pad 4 thru_hole oval (at 0 7.62) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 1 -15V))
(pad 8 thru_hole oval (at 7.62 0) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask))
final fixes for first prototype PCB order
2020-11-12 23:40:18 +00:00
(model ${KISYS3DMOD}/Package_DIP.3dshapes/DIP-8_W7.62mm_Socket.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
Schematic: Bugfixes, VU meter draft, first development PCB draft
2020-11-02 00:00:47 +00:00
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(dimension 60 (width 0.12) (layer Dwgs.User)
(gr_text "60.000 mm" (at 29.73 203 90) (layer Dwgs.User)
(effects (font (size 1 1) (thickness 0.15)))
)
(feature1 (pts (xy 50 173) (xy 30.413579 173)))
(feature2 (pts (xy 50 233) (xy 30.413579 233)))
(crossbar (pts (xy 31 233) (xy 31 173)))
(arrow1a (pts (xy 31 173) (xy 31.586421 174.126504)))
(arrow1b (pts (xy 31 173) (xy 30.413579 174.126504)))
(arrow2a (pts (xy 31 233) (xy 31.586421 231.873496)))
(arrow2b (pts (xy 31 233) (xy 30.413579 231.873496)))
)
(dimension 120 (width 0.12) (layer Dwgs.User)
(gr_text "120.000 mm" (at 29.73 110 90) (layer Dwgs.User)
(effects (font (size 1 1) (thickness 0.15)))
)
(feature1 (pts (xy 50 50) (xy 30.413579 50)))
(feature2 (pts (xy 50 170) (xy 30.413579 170)))
(crossbar (pts (xy 31 170) (xy 31 50)))
(arrow1a (pts (xy 31 50) (xy 31.586421 51.126504)))
(arrow1b (pts (xy 31 50) (xy 30.413579 51.126504)))
(arrow2a (pts (xy 31 170) (xy 31.586421 168.873496)))
(arrow2b (pts (xy 31 170) (xy 30.413579 168.873496)))
)
(dimension 75 (width 0.12) (layer Dwgs.User)
(gr_text "75.000 mm" (at 87.5 25.73) (layer Dwgs.User)
(effects (font (size 1 1) (thickness 0.15)))
)
(feature1 (pts (xy 125 50) (xy 125 26.413579)))
(feature2 (pts (xy 50 50) (xy 50 26.413579)))
(crossbar (pts (xy 50 27) (xy 125 27)))
(arrow1a (pts (xy 125 27) (xy 123.873496 27.586421)))
(arrow1b (pts (xy 125 27) (xy 123.873496 26.413579)))
(arrow2a (pts (xy 50 27) (xy 51.126504 27.586421)))
(arrow2b (pts (xy 50 27) (xy 51.126504 26.413579)))
)
(dimension 37.5 (width 0.12) (layer Dwgs.User)
(gr_text "37.500 mm" (at 68.75 36.73) (layer Dwgs.User)
(effects (font (size 1 1) (thickness 0.15)))
)
(feature1 (pts (xy 50 165) (xy 50 37.413579)))
(feature2 (pts (xy 87.5 165) (xy 87.5 37.413579)))
(crossbar (pts (xy 87.5 38) (xy 50 38)))
(arrow1a (pts (xy 50 38) (xy 51.126504 37.413579)))
(arrow1b (pts (xy 50 38) (xy 51.126504 38.586421)))
(arrow2a (pts (xy 87.5 38) (xy 86.373496 37.413579)))
(arrow2b (pts (xy 87.5 38) (xy 86.373496 38.586421)))
)
(dimension 57 (width 0.12) (layer Dwgs.User)
(gr_text "57.000 mm" (at 78.5 32.73) (layer Dwgs.User)
(effects (font (size 1 1) (thickness 0.15)))
)
(feature1 (pts (xy 107 164) (xy 107 33.413579)))
(feature2 (pts (xy 50 164) (xy 50 33.413579)))
(crossbar (pts (xy 50 34) (xy 107 34)))
(arrow1a (pts (xy 107 34) (xy 105.873496 34.586421)))
(arrow1b (pts (xy 107 34) (xy 105.873496 33.413579)))
(arrow2a (pts (xy 50 34) (xy 51.126504 34.586421)))
(arrow2b (pts (xy 50 34) (xy 51.126504 33.413579)))
)
(gr_line (start 119.5 173) (end 125 173) (layer Edge.Cuts) (width 0.05) (tstamp 60B9ABF8))
(gr_line (start 119.5 170) (end 125 170) (layer Edge.Cuts) (width 0.05) (tstamp 60B9ABF7))
(gr_arc (start 119.5 171.5) (end 119.5 170) (angle -180) (layer Edge.Cuts) (width 0.05))
(gr_arc (start 110.5 171.5) (end 110.5 173) (angle -180) (layer Edge.Cuts) (width 0.05))
(gr_line (start 50 173) (end 55.5 173) (layer Edge.Cuts) (width 0.05) (tstamp 60B9412D))
(gr_line (start 55.5 170) (end 50 170) (layer Edge.Cuts) (width 0.05) (tstamp 60B9412C))
(gr_arc (start 64.5 171.5) (end 64.5 170) (angle -180) (layer Edge.Cuts) (width 0.05))
(gr_arc (start 55.5 171.5) (end 55.5 173) (angle -180) (layer Edge.Cuts) (width 0.05))
(dimension 108 (width 0.12) (layer Dwgs.User)
(gr_text "108.000 mm" (at 36.73 104 90) (layer Dwgs.User)
(effects (font (size 1 1) (thickness 0.15)))
)
(feature1 (pts (xy 107 50) (xy 37.413579 50)))
(feature2 (pts (xy 107 158) (xy 37.413579 158)))
(crossbar (pts (xy 38 158) (xy 38 50)))
(arrow1a (pts (xy 38 50) (xy 38.586421 51.126504)))
(arrow1b (pts (xy 38 50) (xy 37.413579 51.126504)))
(arrow2a (pts (xy 38 158) (xy 38.586421 156.873496)))
(arrow2b (pts (xy 38 158) (xy 37.413579 156.873496)))
)
(dimension 6.5 (width 0.12) (layer Dwgs.User)
(gr_text "6.500 mm" (at 130.27 58.52 90) (layer Dwgs.User)
(effects (font (size 1 1) (thickness 0.15)))
)
(feature1 (pts (xy 83 55.27) (xy 129.586421 55.27)))
(feature2 (pts (xy 83 61.77) (xy 129.586421 61.77)))
(crossbar (pts (xy 129 61.77) (xy 129 55.27)))
(arrow1a (pts (xy 129 55.27) (xy 129.586421 56.396504)))
(arrow1b (pts (xy 129 55.27) (xy 128.413579 56.396504)))
(arrow2a (pts (xy 129 61.77) (xy 129.586421 60.643496)))
(arrow2b (pts (xy 129 61.77) (xy 128.413579 60.643496)))
)
(dimension 5.27 (width 0.12) (layer Dwgs.User)
(gr_text "5.270 mm" (at 134.27 52.635 90) (layer Dwgs.User)
(effects (font (size 1 1) (thickness 0.15)))
)
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2020-11-12 23:40:18 +00:00
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PCB: Channel strip design
2021-05-30 20:24:56 +00:00
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2020-11-12 23:40:18 +00:00
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PCB: Channel strip design
2021-05-30 20:24:56 +00:00
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2020-11-12 23:40:18 +00:00
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PCB: Channel strip design
2021-05-30 20:24:56 +00:00
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2020-11-12 23:40:18 +00:00
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PCB: Channel strip design
2021-05-30 20:24:56 +00:00
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PCB: Channel strip design
2021-05-30 20:24:56 +00:00
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2020-11-12 23:40:18 +00:00
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PCB: Channel strip design
2021-05-30 20:24:56 +00:00
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2020-11-12 23:40:18 +00:00
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PCB: Channel strip design
2021-05-30 20:24:56 +00:00
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PCB: Channel strip design
2021-05-30 20:24:56 +00:00
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2020-11-12 23:40:18 +00:00
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PCB: Channel strip design
2021-05-30 20:24:56 +00:00
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final fixes for first prototype PCB order
2020-11-12 23:40:18 +00:00
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2020-11-12 00:11:14 +00:00
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PCB: Channel strip design
2021-05-30 20:24:56 +00:00
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Schematic: Bugfixes, VU meter draft, first development PCB draft
2020-11-02 00:00:47 +00:00
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final fixes for first prototype PCB order
2020-11-12 23:40:18 +00:00
)
)
(filled_polygon
(pts
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
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Schematic: Bugfixes, VU meter draft, first development PCB draft
2020-11-02 00:00:47 +00:00
)
)
)
PCB: Channel strip design
2021-05-30 20:24:56 +00:00
(zone (net 3) (net_name GND) (layer B.Cu) (tstamp 60B7DB61) (hatch edge 0.508)
Schematic: Bugfixes, VU meter draft, first development PCB draft
2020-11-02 00:00:47 +00:00
(connect_pads (clearance 0.508))
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final fixes for first prototype PCB order
2020-11-12 23:40:18 +00:00
(fill yes (arc_segments 32) (thermal_gap 0.508) (thermal_bridge_width 0.508))
Schematic: Bugfixes, VU meter draft, first development PCB draft
2020-11-02 00:00:47 +00:00
(polygon
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PCB: Channel strip design
2021-05-30 20:24:56 +00:00
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final fixes for first prototype PCB order
2020-11-12 23:40:18 +00:00
)
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PCB: Channel strip design
2021-05-30 20:24:56 +00:00
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Schematic: Bugfixes, VU meter draft, first development PCB draft
2020-11-02 00:00:47 +00:00
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