Schematic: Bugfixes, VU meter draft, first development PCB draft
This commit is contained in:
parent
d1a367d481
commit
6ad73c21d6
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@ -1,32 +1,6 @@
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EESchema-LIBRARY Version 2.4
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#encoding utf-8
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#
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# Amplifier_Audio_LM386
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#
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DEF Amplifier_Audio_LM386 U 0 5 Y Y 1 F N
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F0 "U" 50 300 50 H V L CNN
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F1 "Amplifier_Audio_LM386" 50 200 50 H V L CNN
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F2 "" 100 100 50 H I C CNN
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F3 "" 200 200 50 H I C CNN
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$FPLIST
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SOIC*3.9x4.9mm*P1.27mm*
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DIP*W7.62mm*
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MSSOP*P0.65mm*
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TSSOP*3x3mm*P0.5mm*
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$ENDFPLIST
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DRAW
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P 4 0 1 10 200 0 -200 200 -200 -200 200 0 f
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X GAIN 1 0 -300 200 U 50 20 1 1 I
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X - 2 -300 -100 100 R 50 50 1 1 I
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X + 3 -300 100 100 R 50 50 1 1 I
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X GND 4 -100 -300 150 U 50 50 1 1 W
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X ~ 5 300 0 100 L 50 50 1 1 O
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X V+ 6 -100 300 150 D 50 50 1 1 W
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X BYPASS 7 0 300 200 D 50 20 1 1 I
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X GAIN 8 100 -300 250 U 50 20 1 1 I
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ENDDRAW
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ENDDEF
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#
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# Amplifier_Operational_LM358
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#
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DEF Amplifier_Operational_LM358 U 0 5 Y Y 3 L N
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@ -34,7 +8,7 @@ F0 "U" 0 200 50 H V L CNN
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F1 "Amplifier_Operational_LM358" 0 -200 50 H V L CNN
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F2 "" 0 0 50 H I C CNN
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F3 "" 0 0 50 H I C CNN
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ALIAS LM358 AD8620 LMC6062 LMC6082 TL062 TL072 TL082 NE5532 SA5532 RC4558 RC4560 RC4580 LMV358 TS912 TSV912IDT TSV912IST TLC272 TLC277 MCP602 OPA1678 OPA2134 OPA2340 OPA2376xxD OPA2376xxDGK MC33078 MC33178 LM4562 OP249 OP275 ADA4075-2 MCP6002-xP MCP6002-xSN MCP6002-xMS LM7332 OPA2333xxD OPA2333xxDGK LMC6482 LT1492 LTC6081xMS8 LM6172 MCP6L92 NJM2043 NJM2114 NJM4556A NJM4558 NJM4559 NJM4560 NJM4580 NJM5532 ADA4807-2ARM OPA2691 LT6234 OPA2356xxD OPA2356xxDGK OPA1612AxD MC33172 OPA1602 TLV2372 LT6237 OPA2277 MCP6022
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ALIAS LM358 AD8620 LMC6062 LMC6082 TL062 TL072 TL082 NE5532 SA5532 RC4558 RC4560 RC4580 LMV358 TS912 TSV912IDT TSV912IST TLC272 TLC277 MCP602 OPA1678 OPA2134 OPA2340 OPA2376xxD OPA2376xxDGK MC33078 MC33178 LM4562 OP249 OP275 ADA4075-2 MCP6002-xP MCP6002-xSN MCP6002-xMS LM7332 OPA2333xxD OPA2333xxDGK LMC6482 LT1492 LTC6081xMS8 LM6172 MCP6L92 NJM2043 NJM2114 NJM4556A NJM4558 NJM4559 NJM4560 NJM4580 NJM5532 ADA4807-2ARM OPA2691 LT6234 OPA2356xxD OPA2356xxDGK OPA1612AxD MC33172 OPA1602 TLV2372 LT6237 OPA2277 MCP6022 MCP6V67EMS
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$FPLIST
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SOIC*3.9x4.9mm*P1.27mm*
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DIP*W7.62mm*
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@ -88,6 +62,44 @@ X C/B 8 0 300 200 D 50 20 1 1 I
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ENDDRAW
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ENDDEF
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#
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# Comparator_LM339
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#
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DEF Comparator_LM339 U 0 5 Y Y 5 L N
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F0 "U" 0 200 50 H V L CNN
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F1 "Comparator_LM339" 0 -200 50 H V L CNN
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F2 "" -50 100 50 H I C CNN
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F3 "" 50 200 50 H I C CNN
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ALIAS LMV339
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$FPLIST
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SOIC*3.9x8.7mm*P1.27mm*
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TSSOP*4.4x5mm*P0.65mm*
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$ENDFPLIST
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DRAW
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P 4 1 1 10 -200 200 200 0 -200 -200 -200 200 f
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P 7 1 1 5 130 -20 110 -20 130 0 110 20 90 0 110 -20 90 -20 N
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P 4 2 1 10 -200 200 200 0 -200 -200 -200 200 f
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P 7 2 1 5 130 -20 110 -20 130 0 110 20 90 0 110 -20 90 -20 N
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P 4 3 1 10 -200 200 200 0 -200 -200 -200 200 f
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P 7 3 1 5 130 -20 110 -20 130 0 110 20 90 0 110 -20 90 -20 N
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P 4 4 1 10 -200 200 200 0 -200 -200 -200 200 f
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P 7 4 1 5 130 -20 110 -20 130 0 110 20 90 0 110 -20 90 -20 N
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X ~ 2 300 0 100 L 50 50 1 1 C
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X - 4 -300 -100 100 R 50 50 1 1 I
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X + 5 -300 100 100 R 50 50 1 1 I
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X ~ 1 300 0 100 L 50 50 2 1 C
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X - 6 -300 -100 100 R 50 50 2 1 I
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X + 7 -300 100 100 R 50 50 2 1 I
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X - 10 -300 -100 100 R 50 50 3 1 I
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X + 11 -300 100 100 R 50 50 3 1 I
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X ~ 13 300 0 100 L 50 50 3 1 C
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X ~ 14 300 0 100 L 50 50 4 1 C
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X - 8 -300 -100 100 R 50 50 4 1 I
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X + 9 -300 100 100 R 50 50 4 1 I
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X V- 12 -100 -300 150 U 50 50 5 1 W
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X V+ 3 -100 300 150 D 50 50 5 1 W
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ENDDRAW
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ENDDEF
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#
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# Connector_AudioJack3_Ground
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#
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DEF Connector_AudioJack3_Ground J 0 20 Y Y 1 F N
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@ -200,34 +212,6 @@ X ~ G -100 -300 100 U 50 50 1 1 P
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ENDDRAW
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ENDDEF
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#
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# Converter_ACDC_TMLM04253
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#
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DEF Converter_ACDC_TMLM04253 PS 0 20 Y Y 1 F N
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F0 "PS" 0 250 50 H V C CNN
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F1 "Converter_ACDC_TMLM04253" 0 -250 50 H V C CNN
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F2 "Converter_ACDC:Converter_ACDC_TRACO_TMLM-04_THT" 0 -350 50 H I C CNN
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F3 "" 0 0 50 H I C CNN
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ALIAS TMLM04253
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$FPLIST
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Converter*ACDC*TRACO*TMLM*04*
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$ENDFPLIST
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DRAW
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A -285 38 28 -1525 -275 0 1 0 N -310 25 -260 25
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A -235 11 29 292 1508 0 1 0 N -210 25 -260 25
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S -400 200 400 -200 0 1 10 f
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P 2 0 1 0 -310 -25 -210 -25 N
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P 2 0 1 0 0 -100 0 -150 N
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P 2 0 1 0 0 0 0 -50 N
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P 2 0 1 0 0 100 0 50 N
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P 2 0 1 0 0 200 0 150 N
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X Vout1 2 500 100 100 L 50 50 1 1 w
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X Common 3 500 0 100 L 50 50 1 1 w
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X Vout2 4 500 -100 100 L 50 50 1 1 w
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X AC(L) 5 -500 100 100 R 50 50 1 1 W
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X AC(N) 6 -500 -100 100 R 50 50 1 1 W
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ENDDRAW
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ENDDEF
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#
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# Device_C
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#
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DEF Device_C C 0 10 N Y 1 F N
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ENDDRAW
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ENDDEF
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#
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# Device_D
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#
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DEF Device_D D 0 40 N N 1 F N
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F0 "D" 0 100 50 H V C CNN
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F1 "Device_D" 0 -100 50 H V C CNN
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F2 "" 0 0 50 H I C CNN
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F3 "" 0 0 50 H I C CNN
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$FPLIST
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TO-???*
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*_Diode_*
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*SingleDiode*
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D_*
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$ENDFPLIST
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DRAW
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P 2 0 1 10 -50 50 -50 -50 N
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P 2 0 1 0 50 0 -50 0 N
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P 4 0 1 10 50 50 50 -50 -50 0 50 50 N
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X K 1 -150 0 100 R 50 50 1 1 P
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X A 2 150 0 100 L 50 50 1 1 P
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ENDDRAW
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ENDDEF
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#
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# Device_LED
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#
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DEF Device_LED D 0 40 N N 1 F N
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F0 "D" 0 100 50 H V C CNN
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F1 "Device_LED" 0 -100 50 H V C CNN
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F2 "" 0 0 50 H I C CNN
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F3 "" 0 0 50 H I C CNN
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$FPLIST
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LED*
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LED_SMD:*
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LED_THT:*
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$ENDFPLIST
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DRAW
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P 2 0 1 10 -50 -50 -50 50 N
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P 2 0 1 0 -50 0 50 0 N
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P 4 0 1 10 50 -50 50 50 -50 0 50 -50 N
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P 5 0 1 0 -120 -30 -180 -90 -150 -90 -180 -90 -180 -60 N
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P 5 0 1 0 -70 -30 -130 -90 -100 -90 -130 -90 -130 -60 N
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X K 1 -150 0 100 R 50 50 1 1 P
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X A 2 150 0 100 L 50 50 1 1 P
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ENDDRAW
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ENDDEF
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#
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# Device_R
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#
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DEF Device_R R 0 0 N Y 1 F N
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ENDDRAW
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ENDDEF
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#
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# Switch_SW_Push_Open
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# Jumper_Jumper_3_Bridged12
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#
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DEF Switch_SW_Push_Open SW 0 40 N N 1 F N
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F0 "SW" 0 100 50 H V C CNN
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F1 "Switch_SW_Push_Open" 0 -75 50 H V C CNN
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DEF Jumper_Jumper_3_Bridged12 JP 0 0 Y N 1 F N
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F0 "JP" -100 -100 50 H V C CNN
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F1 "Jumper_Jumper_3_Bridged12" 0 110 50 H V C CNN
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F2 "" 0 0 50 H I C CNN
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F3 "" 0 0 50 H I C CNN
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$FPLIST
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Jumper*
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TestPoint*3Pads*
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TestPoint*Bridge*
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$ENDFPLIST
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DRAW
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A -65 -50 89 1282 518 0 1 0 N -120 20 -10 20
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C -130 0 20 0 0 0 N
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C 0 0 20 0 0 0 N
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C 130 0 20 0 0 0 N
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P 2 0 1 0 0 -50 0 -20 N
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X A 1 -250 0 100 R 50 50 1 1 P
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X C 2 0 -150 100 U 50 50 1 1 I
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X B 3 250 0 100 L 50 50 1 1 P
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ENDDRAW
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ENDDEF
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#
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# Switch_SW_Push
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#
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DEF Switch_SW_Push SW 0 40 N N 1 F N
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F0 "SW" 50 100 50 H V L CNN
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F1 "Switch_SW_Push" 0 -60 50 H V C CNN
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F2 "" 0 200 50 H I C CNN
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F3 "" 0 200 50 H I C CNN
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DRAW
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C -80 0 20 0 1 0 N
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C 80 0 20 0 1 0 N
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P 2 0 1 0 -100 -25 100 -25 N
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P 2 0 1 0 0 -25 0 50 N
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X A 1 -200 0 100 R 50 50 0 1 P
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X B 2 200 0 100 L 50 50 1 1 P
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P 2 0 1 0 0 50 0 120 N
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P 2 0 1 0 100 50 -100 50 N
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X 1 1 -200 0 100 R 50 50 0 1 P
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X 2 2 200 0 100 L 50 50 0 1 P
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ENDDRAW
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ENDDEF
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#
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ENDDRAW
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ENDDEF
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#
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# power_Earth_Protective
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#
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DEF power_Earth_Protective #PWR 0 0 Y Y 1 F P
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F0 "#PWR" 250 -250 50 H I C CNN
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F1 "power_Earth_Protective" 450 -150 50 H I C CNN
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F2 "" 0 -100 50 H I C CNN
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F3 "" 0 -100 50 H I C CNN
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DRAW
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C 0 -150 100 0 1 0 N
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P 2 0 1 0 -25 -175 25 -175 N
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P 2 0 1 0 -5 -200 5 -200 N
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P 2 0 1 0 0 -150 0 0 N
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P 2 0 1 0 50 -150 -50 -150 N
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X Earth_Protective 1 0 0 0 D 50 50 1 1 W N
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ENDDRAW
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ENDDEF
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#
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# power_GNDREF
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#
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DEF power_GNDREF #PWR 0 0 Y Y 1 F P
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File diff suppressed because it is too large
Load diff
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update=Monday, 12 October 2020 at 12:14:27
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update=Sunday, 01 November 2020 at 20:01:52
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last_client=kicad
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[general]
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version=1
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@ -12,3 +12,240 @@ NetFmtName=Pcbnew
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SpiceAjustPassiveValues=0
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LabSize=50
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ERC_TestSimilarLabels=1
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[pcbnew]
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version=1
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PageLayoutDescrFile=
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LastNetListRead=c3lingo-interpreter-unit.net
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CopperLayerCount=2
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BoardThickness=1.6
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AllowMicroVias=0
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AllowBlindVias=0
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RequireCourtyardDefinitions=0
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ProhibitOverlappingCourtyards=1
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MinTrackWidth=0.2
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MinViaDiameter=0.4
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MinViaDrill=0.3
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MinMicroViaDiameter=0.2
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MinMicroViaDrill=0.09999999999999999
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MinHoleToHole=0.25
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TrackWidth1=0.25
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TrackWidth2=0.25
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TrackWidth3=1
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ViaDiameter1=0.6
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ViaDrill1=0.3
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dPairWidth1=0.2
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dPairGap1=0.25
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dPairViaGap1=0.25
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SilkLineWidth=0.12
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SilkTextSizeV=1
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SilkTextSizeH=1
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SilkTextSizeThickness=0.15
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SilkTextItalic=0
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SilkTextUpright=1
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CopperLineWidth=0.2
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CopperTextSizeV=1.5
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CopperTextSizeH=1.5
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CopperTextThickness=0.3
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CopperTextItalic=0
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CopperTextUpright=1
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EdgeCutLineWidth=0.05
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CourtyardLineWidth=0.05
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OthersLineWidth=0.12
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OthersTextSizeV=1
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OthersTextSizeH=1
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OthersTextSizeThickness=0.15
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OthersTextItalic=0
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OthersTextUpright=1
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SolderMaskClearance=0
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SolderMaskMinWidth=0
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SolderPasteClearance=0
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SolderPasteRatio=-0
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[pcbnew/Layer.F.Cu]
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Name=F.Cu
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Type=0
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Enabled=1
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[pcbnew/Layer.In1.Cu]
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Name=In1.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In2.Cu]
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Name=In2.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In3.Cu]
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Name=In3.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In4.Cu]
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Name=In4.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In5.Cu]
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Name=In5.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In6.Cu]
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Name=In6.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In7.Cu]
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Name=In7.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In8.Cu]
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Name=In8.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In9.Cu]
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Name=In9.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In10.Cu]
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Name=In10.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In11.Cu]
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Name=In11.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In12.Cu]
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Name=In12.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In13.Cu]
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Name=In13.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In14.Cu]
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Name=In14.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In15.Cu]
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Name=In15.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In16.Cu]
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Name=In16.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In17.Cu]
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Name=In17.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In18.Cu]
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Name=In18.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In19.Cu]
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Name=In19.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In20.Cu]
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Name=In20.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In21.Cu]
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Name=In21.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In22.Cu]
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Name=In22.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In23.Cu]
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Name=In23.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In24.Cu]
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Name=In24.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In25.Cu]
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Name=In25.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In26.Cu]
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Name=In26.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In27.Cu]
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Name=In27.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In28.Cu]
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Name=In28.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In29.Cu]
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Name=In29.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In30.Cu]
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Name=In30.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.B.Cu]
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||||
Name=B.Cu
|
||||
Type=0
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.Adhes]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.Adhes]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.Paste]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.Paste]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.SilkS]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.SilkS]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.Mask]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.Mask]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Dwgs.User]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Cmts.User]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Eco1.User]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Eco2.User]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Edge.Cuts]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Margin]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.CrtYd]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.CrtYd]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.Fab]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.Fab]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Rescue]
|
||||
Enabled=0
|
||||
[pcbnew/Netclasses]
|
||||
[pcbnew/Netclasses/Default]
|
||||
Name=Default
|
||||
Clearance=0.2
|
||||
TrackWidth=0.25
|
||||
ViaDiameter=0.6
|
||||
ViaDrill=0.3
|
||||
uViaDiameter=0.3
|
||||
uViaDrill=0.1
|
||||
dPairWidth=0.2
|
||||
dPairGap=0.25
|
||||
dPairViaGap=0.25
|
||||
[pcbnew/Netclasses/1]
|
||||
Name=Power
|
||||
Clearance=0.2
|
||||
TrackWidth=1
|
||||
ViaDiameter=0.8
|
||||
ViaDrill=0.6
|
||||
uViaDiameter=0.3
|
||||
uViaDrill=0.1
|
||||
dPairWidth=0.2
|
||||
dPairGap=0.25
|
||||
dPairViaGap=0.25
|
||||
|
|
File diff suppressed because it is too large
Load diff
1223
schematics/vu_meter.sch
Normal file
1223
schematics/vu_meter.sch
Normal file
File diff suppressed because it is too large
Load diff
Reference in a new issue