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c3lingo-interpreter-unit
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final fixes for first prototype PCB order

This commit is contained in:
Jannik Beyerstedt 2020-11-13 00:40:18 +01:00
parent 1432d0e215
commit 6dc353d916
10 changed files with 5979 additions and 5889 deletions
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c3lingo-mixer.pdf
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schematics/mixer/c3lingo-interpreter-unit.kicad_pcb
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schematics/mixer/c3lingo-interpreter-unit.pro
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@ -1,4 +1,4 @@
update=Monday, 09 November 2020 at 23:12:47
update=Thursday, 12 November 2020 at 23:33:32
last_client=kicad
[general]
version=1
@ -219,7 +219,7 @@ Enabled=0
[pcbnew/Netclasses]
[pcbnew/Netclasses/Default]
Name=Default
Clearance=0.2
Clearance=0.25
TrackWidth=0.25
ViaDiameter=0.6
ViaDrill=0.3
@ -230,7 +230,7 @@ dPairGap=0.25
dPairViaGap=0.25
[pcbnew/Netclasses/1]
Name=Power
Clearance=0.2
Clearance=0.3
TrackWidth=1
ViaDiameter=0.8
ViaDrill=0.6

1849
schematics/mixer/c3lingo-interpreter-unit.sch
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schematics/mixer/c3lingo-mixer-gerber-v0.1.zip Normal file
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schematics/vu_meter/vu_meter-gerber-v0.1.zip Normal file
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schematics/vu_meter/vu_meter.kicad_pcb
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schematics/vu_meter/vu_meter.pro
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@ -1,4 +1,4 @@
update=Monday, 09 November 2020 at 23:13:44
update=Thursday, 12 November 2020 at 23:38:27
version=1
last_client=kicad
[general]
@ -12,6 +12,16 @@ NetIExt=net
version=1
LibDir=
[eeschema/libraries]
[schematic_editor]
version=1
PageLayoutDescrFile=
PlotDirectoryName=
SubpartIdSeparator=0
SubpartFirstId=65
NetFmtName=Pcbnew
SpiceAjustPassiveValues=0
LabSize=50
ERC_TestSimilarLabels=1
[pcbnew]
version=1
PageLayoutDescrFile=
@ -229,7 +239,7 @@ Enabled=0
[pcbnew/Netclasses]
[pcbnew/Netclasses/Default]
Name=Default
Clearance=0.2
Clearance=0.25
TrackWidth=0.25
ViaDiameter=0.6
ViaDrill=0.3
@ -240,7 +250,7 @@ dPairGap=0.25
dPairViaGap=0.25
[pcbnew/Netclasses/1]
Name=Power
Clearance=0.2
Clearance=0.3
TrackWidth=1
ViaDiameter=0.8
ViaDrill=0.6
@ -249,13 +259,3 @@ uViaDrill=0.1
dPairWidth=0.2
dPairGap=0.25
dPairViaGap=0.25
[schematic_editor]
version=1
PageLayoutDescrFile=
PlotDirectoryName=
SubpartIdSeparator=0
SubpartFirstId=65
NetFmtName=Pcbnew
SpiceAjustPassiveValues=0
LabSize=50
ERC_TestSimilarLabels=1

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schematics/vu_meter/vu_meter.sch
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@ -5,7 +5,7 @@ $Descr A4 8268 11693 portrait
encoding utf-8
Sheet 1 1
Title "VU Meter Module"
Date "2020-11-08"
Date "2020-11-12"
Rev "v0.1"
Comp "Jannik Beyerstedt"
Comment1 "Experimentation Prototype"
@ -929,7 +929,7 @@ U 1 1 5FD7B3EC
P 4350 9350
F 0 "C6" H 4468 9396 50 0000 L CNN
F 1 "2.2uF" H 4468 9305 50 0000 L CNN
F 2 "Capacitor_THT:CP_Radial_D10.0mm_P5.00mm" H 4388 9200 50 0001 C CNN
F 2 "Capacitor_THT:CP_Radial_D10.0mm_P2.50mm_P5.00mm" H 4388 9200 50 0001 C CNN
F 3 "~" H 4350 9350 50 0001 C CNN
1 4350 9350
1 0 0 -1
@ -1090,7 +1090,7 @@ U 1 1 5FEAE431
P 1750 8250
F 0 "C5" V 2005 8250 50 0000 C CNN
F 1 "10uF" V 1914 8250 50 0000 C CNN
F 2 "Capacitor_THT:CP_Radial_D10.0mm_P5.00mm" H 1788 8100 50 0001 C CNN
F 2 "Capacitor_THT:CP_Radial_D5.0mm_P2.50mm" H 1788 8100 50 0001 C CNN
F 3 "~" H 1750 8250 50 0001 C CNN
1 1750 8250
0 -1 -1 0

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vu_meter.pdf
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