Compare commits
7 Commits
v0.2
...
developmen
| Author | SHA1 | Date |
|---|---|---|
 Jannik Beyerstedt
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04b76dfa98 | |
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Jannik Beyerstedt
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38a8ab0895 | |
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Jannik Beyerstedt
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ae12e7a092 | |
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Jannik Beyerstedt
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b7f3061856 | |
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Jannik Beyerstedt
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65fc825250 | |
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Jannik Beyerstedt
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ce546c151c | |
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Jannik Beyerstedt
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b2358fc77f |
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@ -42,3 +42,5 @@ bom/
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out/
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# End of https://www.toptal.com/developers/gitignore/api/kicad
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*-backups/
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*.kicad_prl
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168
README.md
168
README.md
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@ -48,6 +48,9 @@ This results in a signal flow like this: 
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- [x] First PCB layout (prototyping modules)
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- [x] More testing/ validation
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- [ ] Second PCB layout + casing prototype
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* [x] Channel strip schematic and PCB design
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* [x] Line I/O schematic and PCB design
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* [ ] Power supply
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- [ ] More testing/ validation
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Help is always appreciated!
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@ -77,8 +80,6 @@ For the microphone preamp, we are using the NE5534 low-noise opamp with a circui
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In a normal mixer, you would be able to lower the microphone's volume to zero.
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But in our case we just need on/ off and some gain range to adjust for different microphones and loudness of different people.
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TODO: Integrate the On-Air button with it's LEDs
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### Line Input/ Input Module
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The line input must not be amplified at all, because loudness control of the headphones is done by the headphone amplifier section.
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@ -115,9 +116,14 @@ For the first draft, we're using one LM386 audio power amplifier even though it
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### VU Meter
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When searching for VU meter circuits, many use the LM3916 LED bar graph driver, which already has the right scaling built in.
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But this chip is obsolete and not produced any more, so we designed our own chain of comperators to drive a set of LEDs.
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But this chip is obsolete and not produced any more, so we designed our own chain of comparators to drive a set of LEDs.
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### Phantom Power
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The cheap but still decent Superlux HMC-660 headset is known to sound quite bad with standard 48 V phantom power (which can be easily fixed by adding some resistors inside the XLR connector).
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But when I bought one in April 2021, it worked just fine with 48 V and didn't really work with 12 or 15 V.
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So, if phantom power should be a feature of the interpreter unit, it probably best to have standard 48 V instead of any special treatment for one special headset.
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## User Interface
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The user interface should enable the interpreters to adjust their microphone gain and headphone mix on their own.
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@ -256,75 +262,97 @@ Increasing the voltage by a factor of 10 is an amplification of 20 dB.
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## BoM
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Approximate prices in Euro.
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All prices without VAT and for one piece unless otherwise noted, even if the BOM already asks for more.
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So it's expected to get lower when ordering a full set for multiple units.
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Connectors and Buttons (User Interface)
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#### Line I/O Board Components
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BOM for one PCB, needed 1x for whole assembly.
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Electrolytic capacitors should have 25 V voltage rating, unless otherwise specified.
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| Count | Manufacturer + Art. No. | Description | €/ pc.|
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|-------|--------------------------|----------------------------------|-------|
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| 1 | Neutrik NAC3 MPA-1 | Mains Power Input | 3.33 |
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| 1 | Neutrik NCJ6FA-H | Line Input | 1.27 |
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| 1 | Neutrik NC3MAAH | Line Output | 0.92 |
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| 3x1 | Neutrik NC3FAAV2 | Headset Microphone Input | 1.10 |
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| 3x1 | Rean NYS 216 G | Headphone Output | 0.93 |
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| 3x1 | APEM 1415NC6 | Mute Button (red cap, snap-in) | 3.72 |
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| 3x1 | APEM MHPS2273 | On-Air Button | 0.41 |
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| 3x1 | APEM U4532 | On-Air Button black cap | 0.64 |
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| 3x1 | Alps RK09K1130AJ3 | 10K log Mono Pot. (Gain) | 0.91 |
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| 3x1 | Re'an F311 | Potentiometer Knob | 0.40 |
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| 3x3 | Alps RK09K12C0A2S | 50K log Dual Pot. (Headset Mix) | 1.44 |
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| 3x3 | Re'an P670 | Potentiometer Knob | 0.78 |
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| 3x1 | Alps RK09K1110B1R | 50K log Mono Pot. (Headset Vol.) | 0.67 |
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| 3x1 | Re'an F311 | Potentiometer Knob | 0.40 |
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| 1 | Vishay M64{Y,Z}104 | 100K Trim Pot. | 0.95 |
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| | | **SUM** | 53.99 |
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| Count | Manufacturer + Art. No. | Description | €/ pc.| Distributor Order No.
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|-------|---------------------------|-----------------------------------|-------|----------------------
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| 1 | Neutrik NCJ6FA-H | Stage Line Input | 1.10 | Thomann 250931
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| 1 | Neutrik NC3MAAH | Mix Line Output | 0.78 | Voelkner X39973, Mouser 568-NC3MAAH
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| 1 | PTSM 0,5/ 2-2,5-V THR | PCB Output | 0.50 | Mouser 651-1770953, DigiKey 277-2086-1-ND
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| 1 | PTSM 0,5/ 3-2,5-H THR | PCB PowerSupply | 0.70 | Mouser 651-1770898, DigiKey 277-2080-1-ND
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| 1 | PTSM 0,5/ 4-2,5-V THR | PCB Inputs | 0.80 | Mouser 651-1770979, DigiKey 277-2088-1-ND
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| 1 | Vishay M64Y104 | 100K trim pot: Line input adj. | 0.83 | Reichelt VIS M64Y104KB40
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| 2 | LM833N | Generic Op-Amp | 0.75 | DigiKey 296-44419-5-ND, Mouser 926-LM833N/NOPB
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| 1 | DRV134PA | Line Driver | 4.75 | Mouser 595-DRV134PA, DigiKey DRV134PA-ND
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| 3 | DIP-8 Socket | for LM833N, DRV134PA | 0.03 | Reichelt GS 8
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| 1 | Cer. Cap. 22pF | C_Disc_D5.0mm_W2.5mm_P5.00mm | 0.33 | DigiKey 399-9723-ND, Mouser TODO
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| 1 | Cer. Cap. 47pF | C_Disc_D5.0mm_W2.5mm_P5.00mm | 0.33 | DigiKey 399-C315C470K5G5TA-ND, Mouser TODO
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| 1 | Cer. Cap. 220pF | C_Disc_D5.0mm_W2.5mm_P5.00mm | 0.31 | DigiKey 399-9802-ND, Mouser TODO
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| 6 | Cer. Cap. 100nF | C_Disc_D5.0mm_W2.5mm_P5.00mm | 0.20 | DigiKey 399-4329-ND, Mouser TODO
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| 2 | El. Cap. 10uF | CP_Radial_D5.0mm_P2.00mm | TODO | TODO
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| 6 | 10K | Metal film resistor | 0.02 | Average price at 100 pcs
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| 5 | 22K | Metal film resistor | 0.02 | Average price at 100 pcs
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| 1 | 3.3K | Metal film resistor | 0.02 | Average price at 100 pcs
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| 1 | 47K | Metal film resistor | 0.02 | Average price at 100 pcs
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| | | **SUM** | 13.48 |
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Sub-Components
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| Count | Manufacturer + Art. No. | Description | €/ pc.|
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|-------|--------------------------|----------------------------------|-------|
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| 1 | Traco Power TXL 035-1515D or TOP 60533 | Power Supply | ~48.00 |
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#### Channel Strip Components
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BOM for one PCB, needed 3x for whole assembly.
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Electrolytic capacitors should have 25 V voltage rating, unless otherwise specified.
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PCB Components: TODO when schematic is finished
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| Count | Manufacturer + Art. No. | Description | €/ pc.|
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|-------|--------------------------|----------------------------------|-------|
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| 3 | NE5534 | Low-noise Op-Amp | 0.54 |
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| 8 | LM833 | Generic Op-Amp | 0.88 |
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| 3 | LM386N-4 | Audio Power Amp | 0.83 |
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| 1 | DRV143 | Line Driver | 4.50 |
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| TODO | TODO | El. Capacitor | TODO |
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| TODO | TODO | Cer. Capacitor | TODO |
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| TODO | TODO | Resistor | TODO |
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| | | **SUM** | TODO |
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VU Meter Components
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| Count | Art. No. | Description | €/ pc.|
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|-------|---------------------|---------------------|-------|
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| 1 | Vishay M64{Y,Z}503 | 50K Trim Pot. | 0.95 |
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| 1 | LM833 | Generic Op-Amp | 0.88 |
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| 2 | 1N4148 | Signal Diode | 0.02 |
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| 1 | 1k Metal Film | Resistor | TODO |
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| 1 | 3.9k Metal Film | Resistor | TODO |
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| 1 | 47 uF | El. Capacitor | TODO |
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| 1 | 100k Metal Film | Resistor | TODO |
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| 3 | LM339 | Quad-Ch. Comperator | 0.29 |
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| 5 | 100 nF | Cer. Capacitor | TODO |
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| 1 | 1 uF | El. Capacitor | TODO |
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| 5 | Vishay TLHR 5404 | LED red | 0.18 |
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| 4 | Vishay TLHY 5404 | LED yellow | 0.14 |
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| 3 | Vishay TLHG 5404 | LED green | 0.17 |
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| 12 | 390R | Resistor | TODO |
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| 1 | 39R | Resistor | TODO |
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| 2 | 68R | Resistor | TODO |
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| 1 | 100R | Resistor | TODO |
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| 1 | 150R | Resistor | TODO |
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| 1 | 270R | Resistor | TODO |
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| 1 | 390R | Resistor | TODO |
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| 1 | 680R | Resistor | TODO |
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| 1 | 1K | Resistor | TODO |
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| 1 | 1.5K | Resistor | TODO |
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| 2 | 2.7K | Resistor | TODO |
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| 1 | 3.9K | Resistor | TODO |
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| | | **SUM** | TODO |
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| Count | Model or Art. No. | Description | €/ pc.| Distributor Order No.
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|-------|---------------------------|-----------------------------------|-------|----------------------
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| 1 | Neutrik NC3FAAH2 | Microphone Input | 0.93 | Mouser 568-NC3FAAH-2
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| 1 | Rean NYS 216 or 216G | Headphone Output | 0.51 | Mouser 568-NYS216-U
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| 1 | PTSM 0,5/ 2-2,5-H THR | PCB Output | 0.48 | DigiKey 277-2079-1-ND, Mouser 651-1770885
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| 2 | PTSM 0,5/ 3-2,5-H THR | PCB Interconnect | 0.70 | DigiKey 277-2080-1-ND, Mouser 651-1770898
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| 1 | PTSM 0,5/ 3-2,5-H THR | PCB PowerSupply | 0.70 | DigiKey 277-2080-1-ND, Mouser 651-1770898
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| 1 | PTSM 0,5/ 4-2,5-H THR | PCB PowerSupply | 0.80 | DigiKey 277-2081-1-ND, Mouser 651-1770908
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| 1 | PTSM 0,5/ 4-2,5-H THR | PCB Inputs | 0.80 | DigiKey 277-2081-1-ND, Mouser 651-1770908
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| 3 | Alps RK09K12C0A2S | 50K log. (dual, vert.) Heads. Mix | 1.44 | Mouser 688-RK09K12C0A2S
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| 3 | Davies Molding 1101 | Potentiometer Knob f. Mix | 0.65 | Mouser 5164-1101, DigiKey 1722-1393-ND
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| 1 | Alps RK09K1130AJ3 | 10K log. (single, vert.) Gain | 0.91 | Mouser 688-RK09K1130AJ3
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| 1 | Re'an F311 | Potentiometer Knob f. Gain | 0.35 | Voelkner D18429
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| 1 | Alps RK09K1110B1R | 50K log. (single, horiz.) Vol. | 0.67 | Mouser 688-RK09K1110B1R
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| 1 | Re'an F311 | Potentiometer Knob f. Vol. | 0.35 | Voelkner D18429
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| 1 | Vishay M64Y503 | 50K trim pot: VU meter adj. | 0.83 | Reichelt VIS M64Y503KB40
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| 1 | APEM MHPS2273 | OnAir Switch | 0.41 | Mouser 642-MHPS2273, DigiKey 679-4050-ND
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| 1 | APEM MH15 (alt. U4535) | On-Air Button yellow cap | 0.17 | Mouser 642-MH12
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| 1 | APEM 1415NC6 | Mute Button (red cap, snap-in) | 3.87 | Mouser 642-1415NC6, DigiKey 679-3946-ND
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| 1 | NE5534 | Low-noise Op-Amp | 0.46 | Reichelt NE 5534 DIP
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| 1 | LM386N-4 | Audio Power Amp | 0.80 | Reichelt LM 386N-4 TEX
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| 2 | LM833N | Generic Op-Amp | 0.75 | DigiKey 296-44419-5-ND, Mouser 926-LM833N/NOPB
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| 4 | DIP-8 Socket | for NE5534, LM386N-4, LM833N | 0.03 | Reichelt GS 8
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| 3 | LM339 | Quad Diff. Comparators | 0.26 | Reichelt LM 339 DIL, Mouser 595-LM339N, DigiKey 296-1393-5-ND
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| 1 | DIP-14 Socket | for LM339 | 0.04 | Reichelt GS 14
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| 1 | Cer. Cap. 22pF | C_Disc_D5.0mm_W2.5mm_P5.00mm | 0.33 | DigiKey 399-9723-ND, Mouser TODO
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| 1 | Cer. Cap. 47nF | C_Disc_D5.0mm_W2.5mm_P5.00mm | 0.34 | DigiKey 399-14064-ND, Mouser TODO
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| 11 | Cer. Cap. 100nF | C_Disc_D5.0mm_W2.5mm_P5.00mm | 0.20 | DigiKey 399-4329-ND, Mouser TODO
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| 2 | El. Cap. 1uF | CP_Radial_D5.0mm_P2.00mm | TODO | TODO
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| 2 | El. Cap. 1uF/ 63V, lowESR | CP_Radial_D5.0mm_P2.00mm | TODO | TODO
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| 4 | El. Cap. 100uF | CP_Radial_D6.3mm_P2.50mm | TODO | TODO
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| 1 | El. Cap. 100uF/ 63V | CP_Radial_D10.0mm_P5.00mm | TODO | TODO
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| 1 | El. Cap. 220uF, lowESR | CP_Radial_D6.3mm_P2.50mm | TODO | TODO
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| 3 | Vishay TLHG5405 | LED 5mm, green | 0.14 | Reichelt VIS TLHG 5405
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| 4 | Vishay TLHY5405 | LED 5mm, yellow | 0.21 | Reichelt VIS TLHY 5405
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| 5 | Vishay TLHR5405 | LED 5mm, red | 0.16 | Reichelt VIS TLHR 5405
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| 1 | Vishay TLHR5405 | LED 5mm, On-Air (red) | 0.16 | Reichelt VIS TLHR 5405
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| 6 | 1N4148 | Signal Diode | 0.02 | Reichelt 1N 4148, DigiKey 1N4148FS-ND, Mouser 512-1N4148
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| 5 | 22K | Metal film resistor | 0.02 | Average price at 100 pcs
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| 2 | 330K 1% | Metal film resistor | 0.02 | Average price at 100 pcs
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| 1 | 56R | Metal film resistor | 0.02 | Average price at 100 pcs
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| 1 | 27K 1% | Metal film resistor | 0.02 | Average price at 100 pcs
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| 1 | 330R | Metal film resistor | 0.02 | Average price at 100 pcs
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| 2 | 6.8K 1% | Metal film resistor | 0.02 | Average price at 100 pcs
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| 1 | 330K | Metal film resistor | 0.02 | Average price at 100 pcs
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| 2 | 1K 1% | Metal film resistor | 0.02 | Average price at 100 pcs
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| 1 | 12R | Metal film resistor | 0.02 | Average price at 100 pcs
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| 1 | 2.2K | Metal film resistor | 0.02 | Average price at 100 pcs
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| 2 | 3.9K | Metal film resistor | 0.02 | Average price at 100 pcs
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| 2 | 1K | Metal film resistor | 0.02 | Average price at 100 pcs
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| 2 | 68R | Metal film resistor | 0.02 | Average price at 100 pcs
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| 1 | 39R | Metal film resistor | 0.02 | Average price at 100 pcs
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| 1 | 100R | Metal film resistor | 0.02 | Average price at 100 pcs
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| 1 | 150R | Metal film resistor | 0.02 | Average price at 100 pcs
|
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| 1 | 270R | Metal film resistor | 0.02 | Average price at 100 pcs
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| 13 | 390R | Metal film resistor | 0.02 | Average price at 100 pcs
|
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| 2 | 680R | Metal film resistor | 0.02 | Average price at 100 pcs
|
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| 1 | 1.5K | Metal film resistor | 0.02 | Average price at 100 pcs
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| 2 | 2.7K | Metal film resistor | 0.02 | Average price at 100 pcs
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| | | **SUM** | 29.26 | (without CP for now)
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Load Diff
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@ -0,0 +1,455 @@
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{
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"board": {
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"design_settings": {
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"defaults": {
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"board_outline_line_width": 0.049999999999999996,
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"copper_line_width": 0.19999999999999998,
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"copper_text_italic": false,
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"copper_text_size_h": 1.5,
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"copper_text_size_v": 1.5,
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"copper_text_thickness": 0.3,
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"copper_text_upright": true,
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"courtyard_line_width": 0.049999999999999996,
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"dimension_precision": 4,
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"dimension_units": 3,
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"dimensions": {
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"arrow_length": 1270000,
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||||
"extension_offset": 500000,
|
||||
"keep_text_aligned": true,
|
||||
"suppress_zeroes": false,
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"text_position": 0,
|
||||
"units_format": 1
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||||
},
|
||||
"fab_line_width": 0.09999999999999999,
|
||||
"fab_text_italic": false,
|
||||
"fab_text_size_h": 1.0,
|
||||
"fab_text_size_v": 1.0,
|
||||
"fab_text_thickness": 0.15,
|
||||
"fab_text_upright": false,
|
||||
"other_line_width": 0.12,
|
||||
"other_text_italic": false,
|
||||
"other_text_size_h": 1.0,
|
||||
"other_text_size_v": 1.0,
|
||||
"other_text_thickness": 0.15,
|
||||
"other_text_upright": true,
|
||||
"pads": {
|
||||
"drill": 0.762,
|
||||
"height": 1.524,
|
||||
"width": 1.524
|
||||
},
|
||||
"silk_line_width": 0.12,
|
||||
"silk_text_italic": false,
|
||||
"silk_text_size_h": 1.0,
|
||||
"silk_text_size_v": 1.0,
|
||||
"silk_text_thickness": 0.15,
|
||||
"silk_text_upright": true,
|
||||
"zones": {
|
||||
"45_degree_only": false,
|
||||
"min_clearance": 0.508
|
||||
}
|
||||
},
|
||||
"diff_pair_dimensions": [
|
||||
{
|
||||
"gap": 0.25,
|
||||
"via_gap": 0.25,
|
||||
"width": 0.2
|
||||
}
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||||
],
|
||||
"drc_exclusions": [],
|
||||
"meta": {
|
||||
"version": 2
|
||||
},
|
||||
"rule_severities": {
|
||||
"annular_width": "error",
|
||||
"clearance": "error",
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||||
"copper_edge_clearance": "error",
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||||
"courtyards_overlap": "error",
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||||
"diff_pair_gap_out_of_range": "error",
|
||||
"diff_pair_uncoupled_length_too_long": "error",
|
||||
"drill_out_of_range": "error",
|
||||
"duplicate_footprints": "warning",
|
||||
"extra_footprint": "warning",
|
||||
"footprint_type_mismatch": "error",
|
||||
"hole_clearance": "error",
|
||||
"hole_near_hole": "error",
|
||||
"invalid_outline": "error",
|
||||
"item_on_disabled_layer": "error",
|
||||
"items_not_allowed": "error",
|
||||
"length_out_of_range": "error",
|
||||
"malformed_courtyard": "error",
|
||||
"microvia_drill_out_of_range": "error",
|
||||
"missing_courtyard": "ignore",
|
||||
"missing_footprint": "warning",
|
||||
"net_conflict": "warning",
|
||||
"npth_inside_courtyard": "ignore",
|
||||
"padstack": "error",
|
||||
"pth_inside_courtyard": "ignore",
|
||||
"shorting_items": "error",
|
||||
"silk_over_copper": "warning",
|
||||
"silk_overlap": "warning",
|
||||
"skew_out_of_range": "error",
|
||||
"through_hole_pad_without_hole": "error",
|
||||
"too_many_vias": "error",
|
||||
"track_dangling": "warning",
|
||||
"track_width": "error",
|
||||
"tracks_crossing": "error",
|
||||
"unconnected_items": "error",
|
||||
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File diff suppressed because it is too large
Load Diff
|
|
@ -1,251 +0,0 @@
|
|||
update=Saturday, 29 May 2021 at 00:01:50
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||||
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|
||||
[pcbnew/Layer.Cmts.User]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Eco1.User]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Eco2.User]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Edge.Cuts]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Margin]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.CrtYd]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.CrtYd]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.Fab]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.Fab]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Rescue]
|
||||
Enabled=0
|
||||
[pcbnew/Netclasses]
|
||||
[pcbnew/Netclasses/Default]
|
||||
Name=Default
|
||||
Clearance=0.25
|
||||
TrackWidth=0.25
|
||||
ViaDiameter=0.6
|
||||
ViaDrill=0.3
|
||||
uViaDiameter=0.3
|
||||
uViaDrill=0.1
|
||||
dPairWidth=0.2
|
||||
dPairGap=0.25
|
||||
dPairViaGap=0.25
|
||||
[pcbnew/Netclasses/1]
|
||||
Name=Power
|
||||
Clearance=0.3
|
||||
TrackWidth=1
|
||||
ViaDiameter=0.8
|
||||
ViaDrill=0.6
|
||||
uViaDiameter=0.3
|
||||
uViaDrill=0.1
|
||||
dPairWidth=0.2
|
||||
dPairGap=0.25
|
||||
dPairViaGap=0.25
|
||||
[schematic_editor]
|
||||
version=1
|
||||
PageLayoutDescrFile=
|
||||
PlotDirectoryName=../../
|
||||
SubpartIdSeparator=0
|
||||
SubpartFirstId=65
|
||||
NetFmtName=Pcbnew
|
||||
SpiceAjustPassiveValues=0
|
||||
LabSize=50
|
||||
ERC_TestSimilarLabels=1
|
||||
|
|
@ -1,210 +0,0 @@
|
|||
EESchema Schematic File Version 4
|
||||
EELAYER 30 0
|
||||
EELAYER END
|
||||
$Descr A4 11693 8268
|
||||
encoding utf-8
|
||||
Sheet 1 5
|
||||
Title "c3lingo interpeter unit"
|
||||
Date "2021-05-28"
|
||||
Rev "v0.2"
|
||||
Comp "Jannik Beyerstedt (jtbx)"
|
||||
Comment1 "Prototype 1"
|
||||
Comment2 ""
|
||||
Comment3 ""
|
||||
Comment4 ""
|
||||
$EndDescr
|
||||
$Sheet
|
||||
S 5000 1000 1500 700
|
||||
U 60AE0DAE
|
||||
F0 "Stage Line In + Microphone Mix and Line Out" 50
|
||||
F1 "c3lingo_unit-mix_io/c3lingo_unit-mix_io.sch" 50
|
||||
F2 "StageSignal" O L 5000 1100 50
|
||||
F3 "Mix_Ch1" I L 5000 1300 50
|
||||
F4 "Mix_Ch2" I L 5000 1450 50
|
||||
F5 "Mix_Ch3" I L 5000 1600 50
|
||||
$EndSheet
|
||||
$Sheet
|
||||
S 5000 2250 1500 750
|
||||
U 60AA662F
|
||||
F0 "Mic1 Channel Strip and IO" 50
|
||||
F1 "c3lingo_unit-channel/c3lingo_unit-channel.sch" 50
|
||||
F2 "PreampOut" O L 5000 2350 50
|
||||
F3 "Monitor_OthersA" I L 5000 2750 50
|
||||
F4 "Monitor_OthersB" I L 5000 2900 50
|
||||
F5 "Monitor_Stage" I L 5000 2550 50
|
||||
$EndSheet
|
||||
$Sheet
|
||||
S 5000 3350 1500 750
|
||||
U 60AE7597
|
||||
F0 "Mic2 Channel Strip and IO" 50
|
||||
F1 "c3lingo_unit-channel/c3lingo_unit-channel.sch" 50
|
||||
F2 "PreampOut" O L 5000 3450 50
|
||||
F3 "Monitor_OthersA" I L 5000 3850 50
|
||||
F4 "Monitor_OthersB" I L 5000 4000 50
|
||||
F5 "Monitor_Stage" I L 5000 3650 50
|
||||
$EndSheet
|
||||
$Sheet
|
||||
S 5000 4450 1500 750
|
||||
U 60AE80F3
|
||||
F0 "Mic3 Channel Strip and IO" 50
|
||||
F1 "c3lingo_unit-channel/c3lingo_unit-channel.sch" 50
|
||||
F2 "PreampOut" O L 5000 4550 50
|
||||
F3 "Monitor_OthersA" I L 5000 4950 50
|
||||
F4 "Monitor_OthersB" I L 5000 5100 50
|
||||
F5 "Monitor_Stage" I L 5000 4750 50
|
||||
$EndSheet
|
||||
$Comp
|
||||
L power:GND #PWR0103
|
||||
U 1 1 60AC8130
|
||||
P 6000 7200
|
||||
F 0 "#PWR0103" H 6000 6950 50 0001 C CNN
|
||||
F 1 "GND" H 6005 7027 50 0000 C CNN
|
||||
F 2 "" H 6000 7200 50 0001 C CNN
|
||||
F 3 "" H 6000 7200 50 0001 C CNN
|
||||
1 6000 7200
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L power:+15V #PWR0101
|
||||
U 1 1 60AC8136
|
||||
P 5500 6800
|
||||
F 0 "#PWR0101" H 5500 6650 50 0001 C CNN
|
||||
F 1 "+15V" H 5515 6973 50 0000 C CNN
|
||||
F 2 "" H 5500 6800 50 0001 C CNN
|
||||
F 3 "" H 5500 6800 50 0001 C CNN
|
||||
1 5500 6800
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L power:-15V #PWR0102
|
||||
U 1 1 60AC813C
|
||||
P 5500 7200
|
||||
F 0 "#PWR0102" H 5500 7300 50 0001 C CNN
|
||||
F 1 "-15V" H 5515 7373 50 0000 C CNN
|
||||
F 2 "" H 5500 7200 50 0001 C CNN
|
||||
F 3 "" H 5500 7200 50 0001 C CNN
|
||||
1 5500 7200
|
||||
-1 0 0 1
|
||||
$EndComp
|
||||
$Comp
|
||||
L power:PWR_FLAG #FLG0101
|
||||
U 1 1 60AC8148
|
||||
P 5400 7000
|
||||
F 0 "#FLG0101" H 5400 7075 50 0001 C CNN
|
||||
F 1 "PWR_FLAG" V 5400 7127 50 0000 L CNN
|
||||
F 2 "" H 5400 7000 50 0001 C CNN
|
||||
F 3 "~" H 5400 7000 50 0001 C CNN
|
||||
1 5400 7000
|
||||
0 -1 -1 0
|
||||
$EndComp
|
||||
$Comp
|
||||
L power:PWR_FLAG #FLG0103
|
||||
U 1 1 60AC8154
|
||||
P 6500 7000
|
||||
F 0 "#FLG0103" H 6500 7075 50 0001 C CNN
|
||||
F 1 "PWR_FLAG" H 6500 7173 50 0000 C CNN
|
||||
F 2 "" H 6500 7000 50 0001 C CNN
|
||||
F 3 "~" H 6500 7000 50 0001 C CNN
|
||||
1 6500 7000
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Text Notes 5600 7650 0 50 ~ 0
|
||||
Make the ERC happy
|
||||
$Comp
|
||||
L power:GNDREF #PWR0104
|
||||
U 1 1 632B5377
|
||||
P 6500 7200
|
||||
F 0 "#PWR0104" H 6500 6950 50 0001 C CNN
|
||||
F 1 "GNDREF" H 6505 7027 50 0000 C CNN
|
||||
F 2 "" H 6500 7200 50 0001 C CNN
|
||||
F 3 "" H 6500 7200 50 0001 C CNN
|
||||
1 6500 7200
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
6500 7200 6500 7000
|
||||
Wire Wire Line
|
||||
6000 7000 6000 7200
|
||||
Wire Wire Line
|
||||
5500 6800 5500 7000
|
||||
Wire Wire Line
|
||||
5500 7000 5400 7000
|
||||
Wire Wire Line
|
||||
5500 7000 5500 7200
|
||||
Connection ~ 5500 7000
|
||||
$Comp
|
||||
L power:PWR_FLAG #FLG0102
|
||||
U 1 1 60AC814E
|
||||
P 6000 7000
|
||||
F 0 "#FLG0102" H 6000 7075 50 0001 C CNN
|
||||
F 1 "PWR_FLAG" V 6000 7127 50 0000 L CNN
|
||||
F 2 "" H 6000 7000 50 0001 C CNN
|
||||
F 3 "~" H 6000 7000 50 0001 C CNN
|
||||
1 6000 7000
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
5000 1100 4500 1100
|
||||
Wire Wire Line
|
||||
4500 1100 4500 2550
|
||||
Wire Wire Line
|
||||
4500 2550 5000 2550
|
||||
Wire Wire Line
|
||||
4500 2550 4500 3650
|
||||
Wire Wire Line
|
||||
4500 3650 5000 3650
|
||||
Connection ~ 4500 2550
|
||||
Wire Wire Line
|
||||
4500 3650 4500 4750
|
||||
Wire Wire Line
|
||||
4500 4750 5000 4750
|
||||
Connection ~ 4500 3650
|
||||
Wire Wire Line
|
||||
5000 2350 4200 2350
|
||||
Wire Wire Line
|
||||
4200 2350 4200 1300
|
||||
Wire Wire Line
|
||||
4200 1300 5000 1300
|
||||
Wire Wire Line
|
||||
5000 3450 4050 3450
|
||||
Wire Wire Line
|
||||
4050 3450 4050 2750
|
||||
Wire Wire Line
|
||||
4050 1450 5000 1450
|
||||
Wire Wire Line
|
||||
5000 4550 3900 4550
|
||||
Wire Wire Line
|
||||
3900 4550 3900 4000
|
||||
Wire Wire Line
|
||||
3900 1600 5000 1600
|
||||
Wire Wire Line
|
||||
4200 2350 4200 3850
|
||||
Wire Wire Line
|
||||
4200 3850 5000 3850
|
||||
Connection ~ 4200 2350
|
||||
Wire Wire Line
|
||||
4200 3850 4200 4950
|
||||
Wire Wire Line
|
||||
4200 4950 5000 4950
|
||||
Connection ~ 4200 3850
|
||||
Wire Wire Line
|
||||
4050 3450 4050 5100
|
||||
Wire Wire Line
|
||||
4050 5100 5000 5100
|
||||
Connection ~ 4050 3450
|
||||
Wire Wire Line
|
||||
4050 2750 5000 2750
|
||||
Connection ~ 4050 2750
|
||||
Wire Wire Line
|
||||
4050 2750 4050 1450
|
||||
Wire Wire Line
|
||||
3900 2900 5000 2900
|
||||
Connection ~ 3900 2900
|
||||
Wire Wire Line
|
||||
3900 2900 3900 1600
|
||||
Wire Wire Line
|
||||
5000 4000 3900 4000
|
||||
Connection ~ 3900 4000
|
||||
Wire Wire Line
|
||||
3900 4000 3900 2900
|
||||
$EndSCHEMATC
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,460 @@
|
|||
{
|
||||
"board": {
|
||||
"design_settings": {
|
||||
"defaults": {
|
||||
"board_outline_line_width": 0.049999999999999996,
|
||||
"copper_line_width": 0.19999999999999998,
|
||||
"copper_text_italic": false,
|
||||
"copper_text_size_h": 1.5,
|
||||
"copper_text_size_v": 1.5,
|
||||
"copper_text_thickness": 0.3,
|
||||
"copper_text_upright": false,
|
||||
"courtyard_line_width": 0.049999999999999996,
|
||||
"dimension_precision": 4,
|
||||
"dimension_units": 3,
|
||||
"dimensions": {
|
||||
"arrow_length": 1270000,
|
||||
"extension_offset": 500000,
|
||||
"keep_text_aligned": true,
|
||||
"suppress_zeroes": false,
|
||||
"text_position": 0,
|
||||
"units_format": 1
|
||||
},
|
||||
"fab_line_width": 0.09999999999999999,
|
||||
"fab_text_italic": false,
|
||||
"fab_text_size_h": 1.0,
|
||||
"fab_text_size_v": 1.0,
|
||||
"fab_text_thickness": 0.15,
|
||||
"fab_text_upright": false,
|
||||
"other_line_width": 0.09999999999999999,
|
||||
"other_text_italic": false,
|
||||
"other_text_size_h": 1.0,
|
||||
"other_text_size_v": 1.0,
|
||||
"other_text_thickness": 0.15,
|
||||
"other_text_upright": false,
|
||||
"pads": {
|
||||
"drill": 1.0,
|
||||
"height": 1.7,
|
||||
"width": 1.7
|
||||
},
|
||||
"silk_line_width": 0.12,
|
||||
"silk_text_italic": false,
|
||||
"silk_text_size_h": 1.0,
|
||||
"silk_text_size_v": 1.0,
|
||||
"silk_text_thickness": 0.15,
|
||||
"silk_text_upright": false,
|
||||
"zones": {
|
||||
"45_degree_only": false,
|
||||
"min_clearance": 0.508
|
||||
}
|
||||
},
|
||||
"diff_pair_dimensions": [],
|
||||
"drc_exclusions": [],
|
||||
"meta": {
|
||||
"filename": "board_design_settings.json",
|
||||
"version": 2
|
||||
},
|
||||
"rule_severities": {
|
||||
"annular_width": "error",
|
||||
"clearance": "error",
|
||||
"copper_edge_clearance": "error",
|
||||
"courtyards_overlap": "error",
|
||||
"diff_pair_gap_out_of_range": "error",
|
||||
"diff_pair_uncoupled_length_too_long": "error",
|
||||
"drill_out_of_range": "error",
|
||||
"duplicate_footprints": "warning",
|
||||
"extra_footprint": "warning",
|
||||
"footprint_type_mismatch": "error",
|
||||
"hole_clearance": "error",
|
||||
"hole_near_hole": "error",
|
||||
"invalid_outline": "error",
|
||||
"item_on_disabled_layer": "error",
|
||||
"items_not_allowed": "error",
|
||||
"length_out_of_range": "error",
|
||||
"malformed_courtyard": "error",
|
||||
"microvia_drill_out_of_range": "error",
|
||||
"missing_courtyard": "ignore",
|
||||
"missing_footprint": "warning",
|
||||
"net_conflict": "warning",
|
||||
"npth_inside_courtyard": "ignore",
|
||||
"padstack": "error",
|
||||
"pth_inside_courtyard": "ignore",
|
||||
"shorting_items": "error",
|
||||
"silk_over_copper": "warning",
|
||||
"silk_overlap": "warning",
|
||||
"skew_out_of_range": "error",
|
||||
"through_hole_pad_without_hole": "error",
|
||||
"too_many_vias": "error",
|
||||
"track_dangling": "warning",
|
||||
"track_width": "error",
|
||||
"tracks_crossing": "error",
|
||||
"unconnected_items": "error",
|
||||
"unresolved_variable": "error",
|
||||
"via_dangling": "warning",
|
||||
"zone_has_empty_net": "error",
|
||||
"zones_intersect": "error"
|
||||
},
|
||||
"rules": {
|
||||
"allow_blind_buried_vias": false,
|
||||
"allow_microvias": false,
|
||||
"max_error": 0.005,
|
||||
"min_clearance": 0.0,
|
||||
"min_copper_edge_clearance": 0.024999999999999998,
|
||||
"min_hole_clearance": 0.25,
|
||||
"min_hole_to_hole": 0.25,
|
||||
"min_microvia_diameter": 0.19999999999999998,
|
||||
"min_microvia_drill": 0.09999999999999999,
|
||||
"min_silk_clearance": 0.0,
|
||||
"min_through_hole_diameter": 0.3,
|
||||
"min_track_width": 0.19999999999999998,
|
||||
"min_via_annular_width": 0.049999999999999996,
|
||||
"min_via_diameter": 0.39999999999999997,
|
||||
"use_height_for_length_calcs": true
|
||||
},
|
||||
"track_widths": [
|
||||
0.0,
|
||||
0.25,
|
||||
1.0
|
||||
],
|
||||
"via_dimensions": [
|
||||
{
|
||||
"diameter": 0.0,
|
||||
"drill": 0.0
|
||||
},
|
||||
{
|
||||
"diameter": 0.6,
|
||||
"drill": 0.3
|
||||
},
|
||||
{
|
||||
"diameter": 0.8,
|
||||
"drill": 0.6
|
||||
}
|
||||
],
|
||||
"zones_allow_external_fillets": false,
|
||||
"zones_use_no_outline": true
|
||||
},
|
||||
"layer_presets": []
|
||||
},
|
||||
"boards": [],
|
||||
"cvpcb": {
|
||||
"equivalence_files": []
|
||||
},
|
||||
"erc": {
|
||||
"erc_exclusions": [],
|
||||
"meta": {
|
||||
"version": 0
|
||||
},
|
||||
"pin_map": [
|
||||
[
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
2
|
||||
],
|
||||
[
|
||||
0,
|
||||
2,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2
|
||||
],
|
||||
[
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
1,
|
||||
2
|
||||
],
|
||||
[
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
1,
|
||||
2,
|
||||
1,
|
||||
1,
|
||||
2
|
||||
],
|
||||
[
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
2
|
||||
],
|
||||
[
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
2
|
||||
],
|
||||
[
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
0,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
2
|
||||
],
|
||||
[
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
2
|
||||
],
|
||||
[
|
||||
0,
|
||||
2,
|
||||
1,
|
||||
2,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2
|
||||
],
|
||||
[
|
||||
0,
|
||||
2,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
0,
|
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1,
|
||||
0,
|
||||
2,
|
||||
0,
|
||||
0,
|
||||
2
|
||||
],
|
||||
[
|
||||
0,
|
||||
2,
|
||||
1,
|
||||
1,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
2,
|
||||
0,
|
||||
0,
|
||||
2
|
||||
],
|
||||
[
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2
|
||||
]
|
||||
],
|
||||
"rule_severities": {
|
||||
"bus_definition_conflict": "error",
|
||||
"bus_entry_needed": "error",
|
||||
"bus_label_syntax": "error",
|
||||
"bus_to_bus_conflict": "error",
|
||||
"bus_to_net_conflict": "error",
|
||||
"different_unit_footprint": "error",
|
||||
"different_unit_net": "error",
|
||||
"duplicate_reference": "error",
|
||||
"duplicate_sheet_names": "error",
|
||||
"extra_units": "error",
|
||||
"global_label_dangling": "warning",
|
||||
"hier_label_mismatch": "error",
|
||||
"label_dangling": "error",
|
||||
"lib_symbol_issues": "warning",
|
||||
"multiple_net_names": "warning",
|
||||
"net_not_bus_member": "warning",
|
||||
"no_connect_connected": "warning",
|
||||
"no_connect_dangling": "warning",
|
||||
"pin_not_connected": "error",
|
||||
"pin_not_driven": "error",
|
||||
"pin_to_pin": "warning",
|
||||
"power_pin_not_driven": "error",
|
||||
"similar_labels": "warning",
|
||||
"unannotated": "error",
|
||||
"unit_value_mismatch": "error",
|
||||
"unresolved_variable": "error",
|
||||
"wire_dangling": "error"
|
||||
}
|
||||
},
|
||||
"libraries": {
|
||||
"pinned_footprint_libs": [],
|
||||
"pinned_symbol_libs": []
|
||||
},
|
||||
"meta": {
|
||||
"filename": "c3lingo_unit-channel.kicad_pro",
|
||||
"version": 1
|
||||
},
|
||||
"net_settings": {
|
||||
"classes": [
|
||||
{
|
||||
"bus_width": 12.0,
|
||||
"clearance": 0.25,
|
||||
"diff_pair_gap": 0.25,
|
||||
"diff_pair_via_gap": 0.25,
|
||||
"diff_pair_width": 0.2,
|
||||
"line_style": 0,
|
||||
"microvia_diameter": 0.3,
|
||||
"microvia_drill": 0.1,
|
||||
"name": "Default",
|
||||
"pcb_color": "rgba(0, 0, 0, 0.000)",
|
||||
"schematic_color": "rgba(0, 0, 0, 0.000)",
|
||||
"track_width": 0.25,
|
||||
"via_diameter": 0.6,
|
||||
"via_drill": 0.3,
|
||||
"wire_width": 6.0
|
||||
},
|
||||
{
|
||||
"bus_width": 12.0,
|
||||
"clearance": 0.3,
|
||||
"diff_pair_gap": 0.25,
|
||||
"diff_pair_via_gap": 0.25,
|
||||
"diff_pair_width": 0.2,
|
||||
"line_style": 0,
|
||||
"microvia_diameter": 0.3,
|
||||
"microvia_drill": 0.1,
|
||||
"name": "Power",
|
||||
"nets": [
|
||||
"+15V",
|
||||
"-15V",
|
||||
"GND",
|
||||
"GNDREF",
|
||||
"V_Phant"
|
||||
],
|
||||
"pcb_color": "rgba(0, 0, 0, 0.000)",
|
||||
"schematic_color": "rgba(0, 0, 0, 0.000)",
|
||||
"track_width": 1.0,
|
||||
"via_diameter": 0.8,
|
||||
"via_drill": 0.6,
|
||||
"wire_width": 6.0
|
||||
}
|
||||
],
|
||||
"meta": {
|
||||
"version": 2
|
||||
},
|
||||
"net_colors": null
|
||||
},
|
||||
"pcbnew": {
|
||||
"last_paths": {
|
||||
"gencad": "",
|
||||
"idf": "",
|
||||
"netlist": "../../../../../../../Applications/KiCad/",
|
||||
"specctra_dsn": "",
|
||||
"step": "",
|
||||
"vrml": ""
|
||||
},
|
||||
"page_layout_descr_file": ""
|
||||
},
|
||||
"schematic": {
|
||||
"annotate_start_num": 0,
|
||||
"drawing": {
|
||||
"default_line_thickness": 6.0,
|
||||
"default_text_size": 50.0,
|
||||
"field_names": [],
|
||||
"intersheets_ref_own_page": false,
|
||||
"intersheets_ref_prefix": "",
|
||||
"intersheets_ref_short": false,
|
||||
"intersheets_ref_show": false,
|
||||
"intersheets_ref_suffix": "",
|
||||
"junction_size_choice": 3,
|
||||
"label_size_ratio": 0.375,
|
||||
"pin_symbol_size": 25.0,
|
||||
"text_offset_ratio": 0.15
|
||||
},
|
||||
"legacy_lib_dir": "",
|
||||
"legacy_lib_list": [],
|
||||
"meta": {
|
||||
"version": 1
|
||||
},
|
||||
"net_format_name": "",
|
||||
"ngspice": {
|
||||
"fix_include_paths": true,
|
||||
"fix_passive_vals": false,
|
||||
"meta": {
|
||||
"version": 0
|
||||
},
|
||||
"model_mode": 0,
|
||||
"workbook_filename": ""
|
||||
},
|
||||
"page_layout_descr_file": "",
|
||||
"plot_directory": "",
|
||||
"spice_adjust_passive_values": false,
|
||||
"spice_external_command": "spice \"%I\"",
|
||||
"subpart_first_id": 65,
|
||||
"subpart_id_separator": 0
|
||||
},
|
||||
"sheets": [
|
||||
[
|
||||
"e8e18c84-573e-49d4-a903-1b430b6b9f6d",
|
||||
""
|
||||
]
|
||||
],
|
||||
"text_variables": {}
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,253 +0,0 @@
|
|||
update=Saturday, 29 May 2021 at 23:56:52
|
||||
last_client=kicad
|
||||
[general]
|
||||
version=1
|
||||
[schematic_editor]
|
||||
version=1
|
||||
PageLayoutDescrFile=
|
||||
PlotDirectoryName=../../../
|
||||
SubpartIdSeparator=0
|
||||
SubpartFirstId=65
|
||||
NetFmtName=Pcbnew
|
||||
SpiceAjustPassiveValues=0
|
||||
LabSize=50
|
||||
ERC_TestSimilarLabels=1
|
||||
[pcbnew]
|
||||
version=1
|
||||
PageLayoutDescrFile=
|
||||
LastNetListRead=c3lingo_unit-channel.net
|
||||
CopperLayerCount=2
|
||||
BoardThickness=1.6
|
||||
AllowMicroVias=0
|
||||
AllowBlindVias=0
|
||||
RequireCourtyardDefinitions=0
|
||||
ProhibitOverlappingCourtyards=1
|
||||
MinTrackWidth=0.2
|
||||
MinViaDiameter=0.4
|
||||
MinViaDrill=0.3
|
||||
MinMicroViaDiameter=0.2
|
||||
MinMicroViaDrill=0.09999999999999999
|
||||
MinHoleToHole=0.25
|
||||
TrackWidth1=0.25
|
||||
TrackWidth2=0.25
|
||||
TrackWidth3=1
|
||||
ViaDiameter1=0.6
|
||||
ViaDrill1=0.3
|
||||
ViaDiameter2=0.8
|
||||
ViaDrill2=0.6
|
||||
dPairWidth1=0.2
|
||||
dPairGap1=0.25
|
||||
dPairViaGap1=0.25
|
||||
SilkLineWidth=0.12
|
||||
SilkTextSizeV=1
|
||||
SilkTextSizeH=1
|
||||
SilkTextSizeThickness=0.15
|
||||
SilkTextItalic=0
|
||||
SilkTextUpright=1
|
||||
CopperLineWidth=0.2
|
||||
CopperTextSizeV=1.5
|
||||
CopperTextSizeH=1.5
|
||||
CopperTextThickness=0.3
|
||||
CopperTextItalic=0
|
||||
CopperTextUpright=1
|
||||
EdgeCutLineWidth=0.05
|
||||
CourtyardLineWidth=0.05
|
||||
OthersLineWidth=0.12
|
||||
OthersTextSizeV=1
|
||||
OthersTextSizeH=1
|
||||
OthersTextSizeThickness=0.15
|
||||
OthersTextItalic=0
|
||||
OthersTextUpright=1
|
||||
SolderMaskClearance=0
|
||||
SolderMaskMinWidth=0
|
||||
SolderPasteClearance=0
|
||||
SolderPasteRatio=-0
|
||||
[pcbnew/Layer.F.Cu]
|
||||
Name=F.Cu
|
||||
Type=0
|
||||
Enabled=1
|
||||
[pcbnew/Layer.In1.Cu]
|
||||
Name=In1.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In2.Cu]
|
||||
Name=In2.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In3.Cu]
|
||||
Name=In3.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In4.Cu]
|
||||
Name=In4.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In5.Cu]
|
||||
Name=In5.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In6.Cu]
|
||||
Name=In6.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In7.Cu]
|
||||
Name=In7.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In8.Cu]
|
||||
Name=In8.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In9.Cu]
|
||||
Name=In9.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In10.Cu]
|
||||
Name=In10.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In11.Cu]
|
||||
Name=In11.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In12.Cu]
|
||||
Name=In12.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In13.Cu]
|
||||
Name=In13.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In14.Cu]
|
||||
Name=In14.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In15.Cu]
|
||||
Name=In15.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In16.Cu]
|
||||
Name=In16.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In17.Cu]
|
||||
Name=In17.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In18.Cu]
|
||||
Name=In18.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In19.Cu]
|
||||
Name=In19.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In20.Cu]
|
||||
Name=In20.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In21.Cu]
|
||||
Name=In21.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In22.Cu]
|
||||
Name=In22.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In23.Cu]
|
||||
Name=In23.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In24.Cu]
|
||||
Name=In24.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In25.Cu]
|
||||
Name=In25.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In26.Cu]
|
||||
Name=In26.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In27.Cu]
|
||||
Name=In27.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In28.Cu]
|
||||
Name=In28.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In29.Cu]
|
||||
Name=In29.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In30.Cu]
|
||||
Name=In30.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.B.Cu]
|
||||
Name=B.Cu
|
||||
Type=0
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.Adhes]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.Adhes]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.Paste]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.Paste]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.SilkS]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.SilkS]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.Mask]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.Mask]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Dwgs.User]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Cmts.User]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Eco1.User]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Eco2.User]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Edge.Cuts]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Margin]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.CrtYd]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.CrtYd]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.Fab]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.Fab]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Rescue]
|
||||
Enabled=0
|
||||
[pcbnew/Netclasses]
|
||||
[pcbnew/Netclasses/Default]
|
||||
Name=Default
|
||||
Clearance=0.25
|
||||
TrackWidth=0.25
|
||||
ViaDiameter=0.6
|
||||
ViaDrill=0.3
|
||||
uViaDiameter=0.3
|
||||
uViaDrill=0.1
|
||||
dPairWidth=0.2
|
||||
dPairGap=0.25
|
||||
dPairViaGap=0.25
|
||||
[pcbnew/Netclasses/1]
|
||||
Name=Power
|
||||
Clearance=0.3
|
||||
TrackWidth=1
|
||||
ViaDiameter=0.8
|
||||
ViaDrill=0.6
|
||||
uViaDiameter=0.3
|
||||
uViaDrill=0.1
|
||||
dPairWidth=0.2
|
||||
dPairGap=0.25
|
||||
dPairViaGap=0.25
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,446 @@
|
|||
{
|
||||
"board": {
|
||||
"design_settings": {
|
||||
"defaults": {
|
||||
"board_outline_line_width": 0.049999999999999996,
|
||||
"copper_line_width": 0.19999999999999998,
|
||||
"copper_text_italic": false,
|
||||
"copper_text_size_h": 1.5,
|
||||
"copper_text_size_v": 1.5,
|
||||
"copper_text_thickness": 0.3,
|
||||
"copper_text_upright": false,
|
||||
"courtyard_line_width": 0.049999999999999996,
|
||||
"dimension_precision": 4,
|
||||
"dimension_units": 3,
|
||||
"dimensions": {
|
||||
"arrow_length": 1270000,
|
||||
"extension_offset": 500000,
|
||||
"keep_text_aligned": true,
|
||||
"suppress_zeroes": false,
|
||||
"text_position": 0,
|
||||
"units_format": 1
|
||||
},
|
||||
"fab_line_width": 0.09999999999999999,
|
||||
"fab_text_italic": false,
|
||||
"fab_text_size_h": 1.0,
|
||||
"fab_text_size_v": 1.0,
|
||||
"fab_text_thickness": 0.15,
|
||||
"fab_text_upright": false,
|
||||
"other_line_width": 0.09999999999999999,
|
||||
"other_text_italic": false,
|
||||
"other_text_size_h": 1.0,
|
||||
"other_text_size_v": 1.0,
|
||||
"other_text_thickness": 0.15,
|
||||
"other_text_upright": false,
|
||||
"pads": {
|
||||
"drill": 1.0,
|
||||
"height": 1.7,
|
||||
"width": 1.7
|
||||
},
|
||||
"silk_line_width": 0.12,
|
||||
"silk_text_italic": false,
|
||||
"silk_text_size_h": 1.0,
|
||||
"silk_text_size_v": 1.0,
|
||||
"silk_text_thickness": 0.15,
|
||||
"silk_text_upright": false,
|
||||
"zones": {
|
||||
"45_degree_only": false,
|
||||
"min_clearance": 0.508
|
||||
}
|
||||
},
|
||||
"diff_pair_dimensions": [],
|
||||
"drc_exclusions": [],
|
||||
"meta": {
|
||||
"filename": "board_design_settings.json",
|
||||
"version": 2
|
||||
},
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
"length_out_of_range": "error",
|
||||
"malformed_courtyard": "error",
|
||||
"microvia_drill_out_of_range": "error",
|
||||
"missing_courtyard": "ignore",
|
||||
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|
||||
"net_conflict": "warning",
|
||||
"npth_inside_courtyard": "ignore",
|
||||
"padstack": "error",
|
||||
"pth_inside_courtyard": "ignore",
|
||||
"shorting_items": "error",
|
||||
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|
||||
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|
||||
"skew_out_of_range": "error",
|
||||
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|
||||
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|
||||
"track_dangling": "warning",
|
||||
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|
||||
"tracks_crossing": "error",
|
||||
"unconnected_items": "error",
|
||||
"unresolved_variable": "error",
|
||||
"via_dangling": "warning",
|
||||
"zone_has_empty_net": "error",
|
||||
"zones_intersect": "error"
|
||||
},
|
||||
"rules": {
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
"min_via_diameter": 0.39999999999999997,
|
||||
"use_height_for_length_calcs": true
|
||||
},
|
||||
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|
||||
0.0,
|
||||
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|
||||
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|
||||
],
|
||||
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|
||||
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|
||||
"zones_use_no_outline": true
|
||||
},
|
||||
"layer_presets": []
|
||||
},
|
||||
"boards": [],
|
||||
"cvpcb": {
|
||||
"equivalence_files": []
|
||||
},
|
||||
"erc": {
|
||||
"erc_exclusions": [],
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
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||||
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|
||||
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|
||||
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|
||||
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|
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
],
|
||||
"rule_severities": {
|
||||
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|
||||
"bus_entry_needed": "error",
|
||||
"bus_label_syntax": "error",
|
||||
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|
||||
"bus_to_net_conflict": "error",
|
||||
"different_unit_footprint": "error",
|
||||
"different_unit_net": "error",
|
||||
"duplicate_reference": "error",
|
||||
"duplicate_sheet_names": "error",
|
||||
"extra_units": "error",
|
||||
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|
||||
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|
||||
"label_dangling": "error",
|
||||
"lib_symbol_issues": "warning",
|
||||
"multiple_net_names": "warning",
|
||||
"net_not_bus_member": "warning",
|
||||
"no_connect_connected": "warning",
|
||||
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|
||||
"pin_not_connected": "error",
|
||||
"pin_not_driven": "error",
|
||||
"pin_to_pin": "warning",
|
||||
"power_pin_not_driven": "error",
|
||||
"similar_labels": "warning",
|
||||
"unannotated": "error",
|
||||
"unit_value_mismatch": "error",
|
||||
"unresolved_variable": "error",
|
||||
"wire_dangling": "error"
|
||||
}
|
||||
},
|
||||
"libraries": {
|
||||
"pinned_footprint_libs": [],
|
||||
"pinned_symbol_libs": []
|
||||
},
|
||||
"meta": {
|
||||
"filename": "c3lingo_unit-mix_io.kicad_pro",
|
||||
"version": 1
|
||||
},
|
||||
"net_settings": {
|
||||
"classes": [
|
||||
{
|
||||
"bus_width": 12.0,
|
||||
"clearance": 0.25,
|
||||
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|
||||
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|
||||
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|
||||
"line_style": 0,
|
||||
"microvia_diameter": 0.3,
|
||||
"microvia_drill": 0.1,
|
||||
"name": "Default",
|
||||
"pcb_color": "rgba(0, 0, 0, 0.000)",
|
||||
"schematic_color": "rgba(0, 0, 0, 0.000)",
|
||||
"track_width": 0.25,
|
||||
"via_diameter": 0.6,
|
||||
"via_drill": 0.3,
|
||||
"wire_width": 6.0
|
||||
},
|
||||
{
|
||||
"bus_width": 12.0,
|
||||
"clearance": 0.3,
|
||||
"diff_pair_gap": 0.25,
|
||||
"diff_pair_via_gap": 0.25,
|
||||
"diff_pair_width": 0.2,
|
||||
"line_style": 0,
|
||||
"microvia_diameter": 0.3,
|
||||
"microvia_drill": 0.1,
|
||||
"name": "Power",
|
||||
"nets": [
|
||||
"+15V",
|
||||
"-15V",
|
||||
"GND",
|
||||
"GNDREF"
|
||||
],
|
||||
"pcb_color": "rgba(0, 0, 0, 0.000)",
|
||||
"schematic_color": "rgba(0, 0, 0, 0.000)",
|
||||
"track_width": 1.0,
|
||||
"via_diameter": 0.8,
|
||||
"via_drill": 0.6,
|
||||
"wire_width": 6.0
|
||||
}
|
||||
],
|
||||
"meta": {
|
||||
"version": 2
|
||||
},
|
||||
"net_colors": null
|
||||
},
|
||||
"pcbnew": {
|
||||
"last_paths": {
|
||||
"gencad": "",
|
||||
"idf": "",
|
||||
"netlist": "",
|
||||
"specctra_dsn": "",
|
||||
"step": "",
|
||||
"vrml": ""
|
||||
},
|
||||
"page_layout_descr_file": ""
|
||||
},
|
||||
"schematic": {
|
||||
"annotate_start_num": 0,
|
||||
"drawing": {
|
||||
"default_line_thickness": 6.0,
|
||||
"default_text_size": 50.0,
|
||||
"field_names": [],
|
||||
"intersheets_ref_own_page": false,
|
||||
"intersheets_ref_prefix": "",
|
||||
"intersheets_ref_short": false,
|
||||
"intersheets_ref_show": false,
|
||||
"intersheets_ref_suffix": "",
|
||||
"junction_size_choice": 3,
|
||||
"label_size_ratio": 0.375,
|
||||
"pin_symbol_size": 25.0,
|
||||
"text_offset_ratio": 0.15
|
||||
},
|
||||
"legacy_lib_dir": "",
|
||||
"legacy_lib_list": [],
|
||||
"meta": {
|
||||
"version": 1
|
||||
},
|
||||
"net_format_name": "",
|
||||
"ngspice": {
|
||||
"fix_include_paths": true,
|
||||
"fix_passive_vals": false,
|
||||
"meta": {
|
||||
"version": 0
|
||||
},
|
||||
"model_mode": 0,
|
||||
"workbook_filename": ""
|
||||
},
|
||||
"page_layout_descr_file": "",
|
||||
"plot_directory": "",
|
||||
"spice_adjust_passive_values": false,
|
||||
"spice_external_command": "spice \"%I\"",
|
||||
"subpart_first_id": 65,
|
||||
"subpart_id_separator": 0
|
||||
},
|
||||
"sheets": [
|
||||
[
|
||||
"21e9fedd-b749-4b85-a03a-dffb926d039f",
|
||||
""
|
||||
]
|
||||
],
|
||||
"text_variables": {}
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,253 +0,0 @@
|
|||
update=Saturday, 29 May 2021 at 00:05:13
|
||||
last_client=kicad
|
||||
[general]
|
||||
version=1
|
||||
[schematic_editor]
|
||||
version=1
|
||||
PageLayoutDescrFile=
|
||||
PlotDirectoryName=../../../
|
||||
SubpartIdSeparator=0
|
||||
SubpartFirstId=65
|
||||
NetFmtName=Pcbnew
|
||||
SpiceAjustPassiveValues=0
|
||||
LabSize=50
|
||||
ERC_TestSimilarLabels=1
|
||||
[pcbnew]
|
||||
version=1
|
||||
PageLayoutDescrFile=
|
||||
LastNetListRead=c3lingo_unit-mix_io.net
|
||||
CopperLayerCount=2
|
||||
BoardThickness=1.6
|
||||
AllowMicroVias=0
|
||||
AllowBlindVias=0
|
||||
RequireCourtyardDefinitions=0
|
||||
ProhibitOverlappingCourtyards=1
|
||||
MinTrackWidth=0.2
|
||||
MinViaDiameter=0.4
|
||||
MinViaDrill=0.3
|
||||
MinMicroViaDiameter=0.2
|
||||
MinMicroViaDrill=0.09999999999999999
|
||||
MinHoleToHole=0.25
|
||||
TrackWidth1=0.25
|
||||
TrackWidth2=0.25
|
||||
TrackWidth3=1
|
||||
ViaDiameter1=0.6
|
||||
ViaDrill1=0.3
|
||||
dPairWidth1=0.2
|
||||
ViaDiameter2=0.8
|
||||
ViaDrill2=0.6
|
||||
dPairGap1=0.25
|
||||
dPairViaGap1=0.25
|
||||
SilkLineWidth=0.12
|
||||
SilkTextSizeV=1
|
||||
SilkTextSizeH=1
|
||||
SilkTextSizeThickness=0.15
|
||||
SilkTextItalic=0
|
||||
SilkTextUpright=1
|
||||
CopperLineWidth=0.2
|
||||
CopperTextSizeV=1.5
|
||||
CopperTextSizeH=1.5
|
||||
CopperTextThickness=0.3
|
||||
CopperTextItalic=0
|
||||
CopperTextUpright=1
|
||||
EdgeCutLineWidth=0.05
|
||||
CourtyardLineWidth=0.05
|
||||
OthersLineWidth=0.12
|
||||
OthersTextSizeV=1
|
||||
OthersTextSizeH=1
|
||||
OthersTextSizeThickness=0.15
|
||||
OthersTextItalic=0
|
||||
OthersTextUpright=1
|
||||
SolderMaskClearance=0
|
||||
SolderMaskMinWidth=0
|
||||
SolderPasteClearance=0
|
||||
SolderPasteRatio=-0
|
||||
[pcbnew/Layer.F.Cu]
|
||||
Name=F.Cu
|
||||
Type=0
|
||||
Enabled=1
|
||||
[pcbnew/Layer.In1.Cu]
|
||||
Name=In1.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In2.Cu]
|
||||
Name=In2.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In3.Cu]
|
||||
Name=In3.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In4.Cu]
|
||||
Name=In4.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In5.Cu]
|
||||
Name=In5.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In6.Cu]
|
||||
Name=In6.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In7.Cu]
|
||||
Name=In7.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In8.Cu]
|
||||
Name=In8.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In9.Cu]
|
||||
Name=In9.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In10.Cu]
|
||||
Name=In10.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In11.Cu]
|
||||
Name=In11.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In12.Cu]
|
||||
Name=In12.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In13.Cu]
|
||||
Name=In13.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In14.Cu]
|
||||
Name=In14.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In15.Cu]
|
||||
Name=In15.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In16.Cu]
|
||||
Name=In16.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In17.Cu]
|
||||
Name=In17.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In18.Cu]
|
||||
Name=In18.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In19.Cu]
|
||||
Name=In19.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In20.Cu]
|
||||
Name=In20.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In21.Cu]
|
||||
Name=In21.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In22.Cu]
|
||||
Name=In22.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In23.Cu]
|
||||
Name=In23.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In24.Cu]
|
||||
Name=In24.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In25.Cu]
|
||||
Name=In25.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In26.Cu]
|
||||
Name=In26.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In27.Cu]
|
||||
Name=In27.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In28.Cu]
|
||||
Name=In28.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In29.Cu]
|
||||
Name=In29.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In30.Cu]
|
||||
Name=In30.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.B.Cu]
|
||||
Name=B.Cu
|
||||
Type=0
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.Adhes]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.Adhes]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.Paste]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.Paste]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.SilkS]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.SilkS]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.Mask]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.Mask]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Dwgs.User]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Cmts.User]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Eco1.User]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Eco2.User]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Edge.Cuts]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Margin]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.CrtYd]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.CrtYd]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.Fab]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.Fab]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Rescue]
|
||||
Enabled=0
|
||||
[pcbnew/Netclasses]
|
||||
[pcbnew/Netclasses/Default]
|
||||
Name=Default
|
||||
Clearance=0.25
|
||||
TrackWidth=0.25
|
||||
ViaDiameter=0.6
|
||||
ViaDrill=0.3
|
||||
uViaDiameter=0.3
|
||||
uViaDrill=0.1
|
||||
dPairWidth=0.2
|
||||
dPairGap=0.25
|
||||
dPairViaGap=0.25
|
||||
[pcbnew/Netclasses/1]
|
||||
Name=Power
|
||||
Clearance=0.3
|
||||
TrackWidth=1
|
||||
ViaDiameter=0.8
|
||||
ViaDrill=0.6
|
||||
uViaDiameter=0.3
|
||||
uViaDrill=0.1
|
||||
dPairWidth=0.2
|
||||
dPairGap=0.25
|
||||
dPairViaGap=0.25
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,295 +0,0 @@
|
|||
EESchema-LIBRARY Version 2.4
|
||||
#encoding utf-8
|
||||
#
|
||||
# Amplifier_Operational_LM358
|
||||
#
|
||||
DEF Amplifier_Operational_LM358 U 0 5 Y Y 3 L N
|
||||
F0 "U" 0 200 50 H V L CNN
|
||||
F1 "Amplifier_Operational_LM358" 0 -200 50 H V L CNN
|
||||
F2 "" 0 0 50 H I C CNN
|
||||
F3 "" 0 0 50 H I C CNN
|
||||
ALIAS LM358 AD8620 LMC6062 LMC6082 TL062 TL072 TL082 NE5532 SA5532 RC4558 RC4560 RC4580 LMV358 TS912 TSV912IDT TSV912IST TLC272 TLC277 MCP602 OPA1678 OPA2134 OPA2340 OPA2376xxD OPA2376xxDGK MC33078 MC33178 LM4562 OP249 OP275 ADA4075-2 MCP6002-xP MCP6002-xSN MCP6002-xMS LM7332 OPA2333xxD OPA2333xxDGK LMC6482 LT1492 LTC6081xMS8 LM6172 MCP6L92 NJM2043 NJM2114 NJM4556A NJM4558 NJM4559 NJM4560 NJM4580 NJM5532 ADA4807-2ARM OPA2691 LT6234 OPA2356xxD OPA2356xxDGK OPA1612AxD MC33172 OPA1602 TLV2372 LT6237 OPA2277 MCP6022 MCP6V67EMS
|
||||
$FPLIST
|
||||
SOIC*3.9x4.9mm*P1.27mm*
|
||||
DIP*W7.62mm*
|
||||
TO*99*
|
||||
OnSemi*Micro8*
|
||||
TSSOP*3x3mm*P0.65mm*
|
||||
TSSOP*4.4x3mm*P0.65mm*
|
||||
MSOP*3x3mm*P0.65mm*
|
||||
SSOP*3.9x4.9mm*P0.635mm*
|
||||
LFCSP*2x2mm*P0.5mm*
|
||||
*SIP*
|
||||
SOIC*5.3x6.2mm*P1.27mm*
|
||||
$ENDFPLIST
|
||||
DRAW
|
||||
P 4 1 1 10 -200 200 200 0 -200 -200 -200 200 f
|
||||
P 4 2 1 10 -200 200 200 0 -200 -200 -200 200 f
|
||||
X ~ 1 300 0 100 L 50 50 1 1 O
|
||||
X - 2 -300 -100 100 R 50 50 1 1 I
|
||||
X + 3 -300 100 100 R 50 50 1 1 I
|
||||
X + 5 -300 100 100 R 50 50 2 1 I
|
||||
X - 6 -300 -100 100 R 50 50 2 1 I
|
||||
X ~ 7 300 0 100 L 50 50 2 1 O
|
||||
X V- 4 -100 -300 150 U 50 50 3 1 W
|
||||
X V+ 8 -100 300 150 D 50 50 3 1 W
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# Comparator_LM339
|
||||
#
|
||||
DEF Comparator_LM339 U 0 5 Y Y 5 L N
|
||||
F0 "U" 0 200 50 H V L CNN
|
||||
F1 "Comparator_LM339" 0 -200 50 H V L CNN
|
||||
F2 "" -50 100 50 H I C CNN
|
||||
F3 "" 50 200 50 H I C CNN
|
||||
ALIAS LMV339
|
||||
$FPLIST
|
||||
SOIC*3.9x8.7mm*P1.27mm*
|
||||
TSSOP*4.4x5mm*P0.65mm*
|
||||
$ENDFPLIST
|
||||
DRAW
|
||||
P 4 1 1 10 -200 200 200 0 -200 -200 -200 200 f
|
||||
P 7 1 1 5 130 -20 110 -20 130 0 110 20 90 0 110 -20 90 -20 N
|
||||
P 4 2 1 10 -200 200 200 0 -200 -200 -200 200 f
|
||||
P 7 2 1 5 130 -20 110 -20 130 0 110 20 90 0 110 -20 90 -20 N
|
||||
P 4 3 1 10 -200 200 200 0 -200 -200 -200 200 f
|
||||
P 7 3 1 5 130 -20 110 -20 130 0 110 20 90 0 110 -20 90 -20 N
|
||||
P 4 4 1 10 -200 200 200 0 -200 -200 -200 200 f
|
||||
P 7 4 1 5 130 -20 110 -20 130 0 110 20 90 0 110 -20 90 -20 N
|
||||
X ~ 2 300 0 100 L 50 50 1 1 C
|
||||
X - 4 -300 -100 100 R 50 50 1 1 I
|
||||
X + 5 -300 100 100 R 50 50 1 1 I
|
||||
X ~ 1 300 0 100 L 50 50 2 1 C
|
||||
X - 6 -300 -100 100 R 50 50 2 1 I
|
||||
X + 7 -300 100 100 R 50 50 2 1 I
|
||||
X - 10 -300 -100 100 R 50 50 3 1 I
|
||||
X + 11 -300 100 100 R 50 50 3 1 I
|
||||
X ~ 13 300 0 100 L 50 50 3 1 C
|
||||
X ~ 14 300 0 100 L 50 50 4 1 C
|
||||
X - 8 -300 -100 100 R 50 50 4 1 I
|
||||
X + 9 -300 100 100 R 50 50 4 1 I
|
||||
X V- 12 -100 -300 150 U 50 50 5 1 W
|
||||
X V+ 3 -100 300 150 D 50 50 5 1 W
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# Connector_Conn_01x04_Male
|
||||
#
|
||||
DEF Connector_Conn_01x04_Male J 0 40 Y N 1 F N
|
||||
F0 "J" 0 200 50 H V C CNN
|
||||
F1 "Connector_Conn_01x04_Male" 0 -300 50 H V C CNN
|
||||
F2 "" 0 0 50 H I C CNN
|
||||
F3 "" 0 0 50 H I C CNN
|
||||
$FPLIST
|
||||
Connector*:*_1x??_*
|
||||
$ENDFPLIST
|
||||
DRAW
|
||||
S 34 -195 0 -205 1 1 6 F
|
||||
S 34 -95 0 -105 1 1 6 F
|
||||
S 34 5 0 -5 1 1 6 F
|
||||
S 34 105 0 95 1 1 6 F
|
||||
P 2 1 1 6 50 -200 34 -200 N
|
||||
P 2 1 1 6 50 -100 34 -100 N
|
||||
P 2 1 1 6 50 0 34 0 N
|
||||
P 2 1 1 6 50 100 34 100 N
|
||||
X Pin_1 1 200 100 150 L 50 50 1 1 P
|
||||
X Pin_2 2 200 0 150 L 50 50 1 1 P
|
||||
X Pin_3 3 200 -100 150 L 50 50 1 1 P
|
||||
X Pin_4 4 200 -200 150 L 50 50 1 1 P
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# Device_C
|
||||
#
|
||||
DEF Device_C C 0 10 N Y 1 F N
|
||||
F0 "C" 25 100 50 H V L CNN
|
||||
F1 "Device_C" 25 -100 50 H V L CNN
|
||||
F2 "" 38 -150 50 H I C CNN
|
||||
F3 "" 0 0 50 H I C CNN
|
||||
$FPLIST
|
||||
C_*
|
||||
$ENDFPLIST
|
||||
DRAW
|
||||
P 2 0 1 20 -80 -30 80 -30 N
|
||||
P 2 0 1 20 -80 30 80 30 N
|
||||
X ~ 1 0 150 110 D 50 50 1 1 P
|
||||
X ~ 2 0 -150 110 U 50 50 1 1 P
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# Device_CP
|
||||
#
|
||||
DEF Device_CP C 0 10 N Y 1 F N
|
||||
F0 "C" 25 100 50 H V L CNN
|
||||
F1 "Device_CP" 25 -100 50 H V L CNN
|
||||
F2 "" 38 -150 50 H I C CNN
|
||||
F3 "" 0 0 50 H I C CNN
|
||||
$FPLIST
|
||||
CP_*
|
||||
$ENDFPLIST
|
||||
DRAW
|
||||
S -90 20 90 40 0 1 0 N
|
||||
S 90 -20 -90 -40 0 1 0 F
|
||||
P 2 0 1 0 -70 90 -30 90 N
|
||||
P 2 0 1 0 -50 110 -50 70 N
|
||||
X ~ 1 0 150 110 D 50 50 1 1 P
|
||||
X ~ 2 0 -150 110 U 50 50 1 1 P
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# Device_D
|
||||
#
|
||||
DEF Device_D D 0 40 N N 1 F N
|
||||
F0 "D" 0 100 50 H V C CNN
|
||||
F1 "Device_D" 0 -100 50 H V C CNN
|
||||
F2 "" 0 0 50 H I C CNN
|
||||
F3 "" 0 0 50 H I C CNN
|
||||
$FPLIST
|
||||
TO-???*
|
||||
*_Diode_*
|
||||
*SingleDiode*
|
||||
D_*
|
||||
$ENDFPLIST
|
||||
DRAW
|
||||
P 2 0 1 10 -50 50 -50 -50 N
|
||||
P 2 0 1 0 50 0 -50 0 N
|
||||
P 4 0 1 10 50 50 50 -50 -50 0 50 50 N
|
||||
X K 1 -150 0 100 R 50 50 1 1 P
|
||||
X A 2 150 0 100 L 50 50 1 1 P
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# Device_LED
|
||||
#
|
||||
DEF Device_LED D 0 40 N N 1 F N
|
||||
F0 "D" 0 100 50 H V C CNN
|
||||
F1 "Device_LED" 0 -100 50 H V C CNN
|
||||
F2 "" 0 0 50 H I C CNN
|
||||
F3 "" 0 0 50 H I C CNN
|
||||
$FPLIST
|
||||
LED*
|
||||
LED_SMD:*
|
||||
LED_THT:*
|
||||
$ENDFPLIST
|
||||
DRAW
|
||||
P 2 0 1 10 -50 -50 -50 50 N
|
||||
P 2 0 1 0 -50 0 50 0 N
|
||||
P 4 0 1 10 50 -50 50 50 -50 0 50 -50 N
|
||||
P 5 0 1 0 -120 -30 -180 -90 -150 -90 -180 -90 -180 -60 N
|
||||
P 5 0 1 0 -70 -30 -130 -90 -100 -90 -130 -90 -130 -60 N
|
||||
X K 1 -150 0 100 R 50 50 1 1 P
|
||||
X A 2 150 0 100 L 50 50 1 1 P
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# Device_R
|
||||
#
|
||||
DEF Device_R R 0 0 N Y 1 F N
|
||||
F0 "R" 80 0 50 V V C CNN
|
||||
F1 "Device_R" 0 0 50 V V C CNN
|
||||
F2 "" -70 0 50 V I C CNN
|
||||
F3 "" 0 0 50 H I C CNN
|
||||
$FPLIST
|
||||
R_*
|
||||
$ENDFPLIST
|
||||
DRAW
|
||||
S -40 -100 40 100 0 1 10 N
|
||||
X ~ 1 0 150 50 D 50 50 1 1 P
|
||||
X ~ 2 0 -150 50 U 50 50 1 1 P
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# Device_R_POT
|
||||
#
|
||||
DEF Device_R_POT RV 0 40 Y N 1 F N
|
||||
F0 "RV" -175 0 50 V V C CNN
|
||||
F1 "Device_R_POT" -100 0 50 V V C CNN
|
||||
F2 "" 0 0 50 H I C CNN
|
||||
F3 "" 0 0 50 H I C CNN
|
||||
$FPLIST
|
||||
Potentiometer*
|
||||
$ENDFPLIST
|
||||
DRAW
|
||||
S 40 100 -40 -100 0 1 10 N
|
||||
P 2 0 1 0 100 0 60 0 N
|
||||
P 4 0 1 0 45 0 90 20 90 -20 45 0 F
|
||||
X 1 1 0 150 50 D 50 50 1 1 P
|
||||
X 2 2 150 0 50 L 50 50 1 1 P
|
||||
X 3 3 0 -150 50 U 50 50 1 1 P
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# Mechanical_MountingHole
|
||||
#
|
||||
DEF Mechanical_MountingHole H 0 40 Y Y 1 F N
|
||||
F0 "H" 0 200 50 H V C CNN
|
||||
F1 "Mechanical_MountingHole" 0 125 50 H V C CNN
|
||||
F2 "" 0 0 50 H I C CNN
|
||||
F3 "" 0 0 50 H I C CNN
|
||||
$FPLIST
|
||||
MountingHole*
|
||||
$ENDFPLIST
|
||||
DRAW
|
||||
C 0 0 50 0 1 50 N
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# power_+15V
|
||||
#
|
||||
DEF power_+15V #PWR 0 0 Y Y 1 F P
|
||||
F0 "#PWR" 0 -150 50 H I C CNN
|
||||
F1 "power_+15V" 0 140 50 H V C CNN
|
||||
F2 "" 0 0 50 H I C CNN
|
||||
F3 "" 0 0 50 H I C CNN
|
||||
DRAW
|
||||
P 2 0 1 0 -30 50 0 100 N
|
||||
P 2 0 1 0 0 0 0 100 N
|
||||
P 2 0 1 0 0 100 30 50 N
|
||||
X +15V 1 0 0 0 U 50 50 1 1 W N
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# power_-15V
|
||||
#
|
||||
DEF power_-15V #PWR 0 0 Y Y 1 F P
|
||||
F0 "#PWR" 0 100 50 H I C CNN
|
||||
F1 "power_-15V" 0 150 50 H V C CNN
|
||||
F2 "" 0 0 50 H I C CNN
|
||||
F3 "" 0 0 50 H I C CNN
|
||||
DRAW
|
||||
P 6 0 1 0 0 0 0 50 30 50 0 100 -30 50 0 50 F
|
||||
X -15V 1 0 0 0 U 50 50 0 0 W N
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# power_GNDREF
|
||||
#
|
||||
DEF power_GNDREF #PWR 0 0 Y Y 1 F P
|
||||
F0 "#PWR" 0 -250 50 H I C CNN
|
||||
F1 "power_GNDREF" 0 -150 50 H V C CNN
|
||||
F2 "" 0 0 50 H I C CNN
|
||||
F3 "" 0 0 50 H I C CNN
|
||||
DRAW
|
||||
P 2 0 1 0 -25 -75 25 -75 N
|
||||
P 2 0 1 0 -5 -100 5 -100 N
|
||||
P 2 0 1 0 0 -50 0 0 N
|
||||
P 2 0 1 0 50 -50 -50 -50 N
|
||||
X GNDREF 1 0 0 0 D 50 50 1 1 W N
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# power_PWR_FLAG
|
||||
#
|
||||
DEF power_PWR_FLAG #FLG 0 0 N N 1 F P
|
||||
F0 "#FLG" 0 75 50 H I C CNN
|
||||
F1 "power_PWR_FLAG" 0 150 50 H V C CNN
|
||||
F2 "" 0 0 50 H I C CNN
|
||||
F3 "" 0 0 50 H I C CNN
|
||||
DRAW
|
||||
P 6 0 1 0 0 0 0 50 -40 75 0 100 40 75 0 50 N
|
||||
X pwr 1 0 0 0 U 50 50 0 0 w
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
#End Library
|
||||
Binary file not shown.
Binary file not shown.
File diff suppressed because it is too large
Load Diff
|
|
@ -1,261 +0,0 @@
|
|||
update=Sunday, 13 December 2020 at 21:47:42
|
||||
version=1
|
||||
last_client=kicad
|
||||
[general]
|
||||
version=1
|
||||
RootSch=
|
||||
BoardNm=
|
||||
[cvpcb]
|
||||
version=1
|
||||
NetIExt=net
|
||||
[eeschema]
|
||||
version=1
|
||||
LibDir=
|
||||
[eeschema/libraries]
|
||||
[pcbnew]
|
||||
version=1
|
||||
PageLayoutDescrFile=
|
||||
LastNetListRead=vu_meter.net
|
||||
CopperLayerCount=2
|
||||
BoardThickness=1.6
|
||||
AllowMicroVias=0
|
||||
AllowBlindVias=0
|
||||
RequireCourtyardDefinitions=0
|
||||
ProhibitOverlappingCourtyards=1
|
||||
MinTrackWidth=0.2
|
||||
MinViaDiameter=0.4
|
||||
MinViaDrill=0.3
|
||||
MinMicroViaDiameter=0.2
|
||||
MinMicroViaDrill=0.09999999999999999
|
||||
MinHoleToHole=0.25
|
||||
TrackWidth1=0.25
|
||||
TrackWidth2=0.25
|
||||
TrackWidth3=1
|
||||
ViaDiameter1=0.6
|
||||
ViaDrill1=0.3
|
||||
dPairWidth1=0.2
|
||||
dPairGap1=0.25
|
||||
dPairViaGap1=0.25
|
||||
SilkLineWidth=0.12
|
||||
SilkTextSizeV=1
|
||||
SilkTextSizeH=1
|
||||
SilkTextSizeThickness=0.15
|
||||
SilkTextItalic=0
|
||||
SilkTextUpright=1
|
||||
CopperLineWidth=0.2
|
||||
CopperTextSizeV=1.5
|
||||
CopperTextSizeH=1.5
|
||||
CopperTextThickness=0.3
|
||||
CopperTextItalic=0
|
||||
CopperTextUpright=1
|
||||
EdgeCutLineWidth=0.05
|
||||
CourtyardLineWidth=0.05
|
||||
OthersLineWidth=0.12
|
||||
OthersTextSizeV=1
|
||||
OthersTextSizeH=1
|
||||
OthersTextSizeThickness=0.15
|
||||
OthersTextItalic=0
|
||||
OthersTextUpright=1
|
||||
SolderMaskClearance=0
|
||||
SolderMaskMinWidth=0
|
||||
SolderPasteClearance=0
|
||||
SolderPasteRatio=-0
|
||||
[pcbnew/Layer.F.Cu]
|
||||
Name=F.Cu
|
||||
Type=0
|
||||
Enabled=1
|
||||
[pcbnew/Layer.In1.Cu]
|
||||
Name=In1.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In2.Cu]
|
||||
Name=In2.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In3.Cu]
|
||||
Name=In3.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In4.Cu]
|
||||
Name=In4.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In5.Cu]
|
||||
Name=In5.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In6.Cu]
|
||||
Name=In6.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In7.Cu]
|
||||
Name=In7.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In8.Cu]
|
||||
Name=In8.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In9.Cu]
|
||||
Name=In9.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In10.Cu]
|
||||
Name=In10.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In11.Cu]
|
||||
Name=In11.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In12.Cu]
|
||||
Name=In12.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In13.Cu]
|
||||
Name=In13.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In14.Cu]
|
||||
Name=In14.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In15.Cu]
|
||||
Name=In15.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In16.Cu]
|
||||
Name=In16.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In17.Cu]
|
||||
Name=In17.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In18.Cu]
|
||||
Name=In18.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In19.Cu]
|
||||
Name=In19.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In20.Cu]
|
||||
Name=In20.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In21.Cu]
|
||||
Name=In21.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In22.Cu]
|
||||
Name=In22.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In23.Cu]
|
||||
Name=In23.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In24.Cu]
|
||||
Name=In24.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In25.Cu]
|
||||
Name=In25.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In26.Cu]
|
||||
Name=In26.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In27.Cu]
|
||||
Name=In27.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In28.Cu]
|
||||
Name=In28.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In29.Cu]
|
||||
Name=In29.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In30.Cu]
|
||||
Name=In30.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.B.Cu]
|
||||
Name=B.Cu
|
||||
Type=0
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.Adhes]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.Adhes]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.Paste]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.Paste]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.SilkS]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.SilkS]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.Mask]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.Mask]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Dwgs.User]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Cmts.User]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Eco1.User]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Eco2.User]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Edge.Cuts]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Margin]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.CrtYd]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.CrtYd]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.Fab]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.Fab]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Rescue]
|
||||
Enabled=0
|
||||
[pcbnew/Netclasses]
|
||||
[pcbnew/Netclasses/Default]
|
||||
Name=Default
|
||||
Clearance=0.25
|
||||
TrackWidth=0.25
|
||||
ViaDiameter=0.6
|
||||
ViaDrill=0.3
|
||||
uViaDiameter=0.3
|
||||
uViaDrill=0.1
|
||||
dPairWidth=0.2
|
||||
dPairGap=0.25
|
||||
dPairViaGap=0.25
|
||||
[pcbnew/Netclasses/1]
|
||||
Name=Power
|
||||
Clearance=0.3
|
||||
TrackWidth=1
|
||||
ViaDiameter=0.8
|
||||
ViaDrill=0.6
|
||||
uViaDiameter=0.3
|
||||
uViaDrill=0.1
|
||||
dPairWidth=0.2
|
||||
dPairGap=0.25
|
||||
dPairViaGap=0.25
|
||||
[schematic_editor]
|
||||
version=1
|
||||
PageLayoutDescrFile=
|
||||
PlotDirectoryName=../../
|
||||
SubpartIdSeparator=0
|
||||
SubpartFirstId=65
|
||||
NetFmtName=Pcbnew
|
||||
SpiceAjustPassiveValues=0
|
||||
LabSize=50
|
||||
ERC_TestSimilarLabels=1
|
||||
File diff suppressed because it is too large
Load Diff
BIN
vu_meter.pdf
BIN
vu_meter.pdf
Binary file not shown.
Reference in New Issue