final fixes for first prototype PCB order
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1432d0e215
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@ -1,4 +1,4 @@
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update=Monday, 09 November 2020 at 23:12:47
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update=Thursday, 12 November 2020 at 23:33:32
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last_client=kicad
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last_client=kicad
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[general]
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[general]
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version=1
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version=1
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@ -219,7 +219,7 @@ Enabled=0
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[pcbnew/Netclasses]
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[pcbnew/Netclasses]
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[pcbnew/Netclasses/Default]
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[pcbnew/Netclasses/Default]
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Name=Default
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Name=Default
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Clearance=0.2
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Clearance=0.25
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TrackWidth=0.25
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TrackWidth=0.25
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ViaDiameter=0.6
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ViaDiameter=0.6
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ViaDrill=0.3
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ViaDrill=0.3
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@ -230,7 +230,7 @@ dPairGap=0.25
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dPairViaGap=0.25
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dPairViaGap=0.25
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[pcbnew/Netclasses/1]
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[pcbnew/Netclasses/1]
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Name=Power
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Name=Power
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Clearance=0.2
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Clearance=0.3
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TrackWidth=1
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TrackWidth=1
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ViaDiameter=0.8
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ViaDiameter=0.8
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ViaDrill=0.6
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ViaDrill=0.6
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schematics/mixer/c3lingo-mixer-gerber-v0.1.zip
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schematics/mixer/c3lingo-mixer-gerber-v0.1.zip
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schematics/vu_meter/vu_meter-gerber-v0.1.zip
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schematics/vu_meter/vu_meter-gerber-v0.1.zip
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update=Monday, 09 November 2020 at 23:13:44
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update=Thursday, 12 November 2020 at 23:38:27
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version=1
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version=1
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last_client=kicad
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last_client=kicad
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[general]
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[general]
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@ -12,6 +12,16 @@ NetIExt=net
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version=1
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version=1
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LibDir=
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LibDir=
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[eeschema/libraries]
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[eeschema/libraries]
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[schematic_editor]
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version=1
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PageLayoutDescrFile=
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PlotDirectoryName=
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SubpartIdSeparator=0
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SubpartFirstId=65
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NetFmtName=Pcbnew
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SpiceAjustPassiveValues=0
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LabSize=50
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ERC_TestSimilarLabels=1
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[pcbnew]
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[pcbnew]
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version=1
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version=1
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PageLayoutDescrFile=
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PageLayoutDescrFile=
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@ -229,7 +239,7 @@ Enabled=0
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[pcbnew/Netclasses]
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[pcbnew/Netclasses]
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[pcbnew/Netclasses/Default]
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[pcbnew/Netclasses/Default]
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Name=Default
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Name=Default
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Clearance=0.2
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Clearance=0.25
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TrackWidth=0.25
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TrackWidth=0.25
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ViaDiameter=0.6
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ViaDiameter=0.6
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ViaDrill=0.3
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ViaDrill=0.3
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@ -240,7 +250,7 @@ dPairGap=0.25
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dPairViaGap=0.25
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dPairViaGap=0.25
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[pcbnew/Netclasses/1]
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[pcbnew/Netclasses/1]
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Name=Power
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Name=Power
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Clearance=0.2
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Clearance=0.3
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TrackWidth=1
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TrackWidth=1
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ViaDiameter=0.8
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ViaDiameter=0.8
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ViaDrill=0.6
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ViaDrill=0.6
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@ -249,13 +259,3 @@ uViaDrill=0.1
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dPairWidth=0.2
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dPairWidth=0.2
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dPairGap=0.25
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dPairGap=0.25
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dPairViaGap=0.25
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dPairViaGap=0.25
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[schematic_editor]
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version=1
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PageLayoutDescrFile=
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PlotDirectoryName=
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SubpartIdSeparator=0
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SubpartFirstId=65
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NetFmtName=Pcbnew
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SpiceAjustPassiveValues=0
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LabSize=50
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ERC_TestSimilarLabels=1
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@ -5,7 +5,7 @@ $Descr A4 8268 11693 portrait
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encoding utf-8
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encoding utf-8
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Sheet 1 1
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Sheet 1 1
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Title "VU Meter Module"
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Title "VU Meter Module"
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Date "2020-11-08"
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Date "2020-11-12"
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Rev "v0.1"
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Rev "v0.1"
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Comp "Jannik Beyerstedt"
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Comp "Jannik Beyerstedt"
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Comment1 "Experimentation Prototype"
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Comment1 "Experimentation Prototype"
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@ -929,7 +929,7 @@ U 1 1 5FD7B3EC
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P 4350 9350
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P 4350 9350
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F 0 "C6" H 4468 9396 50 0000 L CNN
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F 0 "C6" H 4468 9396 50 0000 L CNN
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F 1 "2.2uF" H 4468 9305 50 0000 L CNN
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F 1 "2.2uF" H 4468 9305 50 0000 L CNN
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F 2 "Capacitor_THT:CP_Radial_D10.0mm_P5.00mm" H 4388 9200 50 0001 C CNN
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F 2 "Capacitor_THT:CP_Radial_D10.0mm_P2.50mm_P5.00mm" H 4388 9200 50 0001 C CNN
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F 3 "~" H 4350 9350 50 0001 C CNN
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F 3 "~" H 4350 9350 50 0001 C CNN
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1 4350 9350
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1 4350 9350
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1 0 0 -1
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1 0 0 -1
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@ -1090,7 +1090,7 @@ U 1 1 5FEAE431
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P 1750 8250
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P 1750 8250
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F 0 "C5" V 2005 8250 50 0000 C CNN
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F 0 "C5" V 2005 8250 50 0000 C CNN
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F 1 "10uF" V 1914 8250 50 0000 C CNN
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F 1 "10uF" V 1914 8250 50 0000 C CNN
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F 2 "Capacitor_THT:CP_Radial_D10.0mm_P5.00mm" H 1788 8100 50 0001 C CNN
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F 2 "Capacitor_THT:CP_Radial_D5.0mm_P2.50mm" H 1788 8100 50 0001 C CNN
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F 3 "~" H 1750 8250 50 0001 C CNN
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F 3 "~" H 1750 8250 50 0001 C CNN
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1 1750 8250
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1 1750 8250
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0 -1 -1 0
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0 -1 -1 0
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vu_meter.pdf
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vu_meter.pdf
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